Semiconductor integrated circuit device and fabrication method for semiconductor integrated circuit device

ABSTRACT

Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed using the Damascene method, and after a post-CMP cleaning step, the surface of the silicon oxide film and Cu interconnections is treated by a reducing plasma (ammonia plasma). Subsequently, a continuous cap film (silicon nitride film) is formed without vacuum break.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation application of U.S. Ser. No.10/811,927, filed Mar. 30, 2004, which is a continuation application ofU.S. Ser. No. 09/825,946, filed Apr. 5, 2001, the contents of which areincorporated herein by reference.

BACKGROUND OF THE INVENTION

This invention relates to a method of fabricating a semiconductorintegrated circuit device, to a semiconductor integrated circuit devicetechnique; and, in particular, to a method of fabricating asemiconductor integrated circuit device comprising an embeddedinterconnection having copper as the main conducting layer, and aneffective technique applied to a semiconductor integrated circuitdevice.

In a technique for forming interconnections comprising semiconductorintegrated circuit devices, semiconductor devices, electronic circuitdevices and electronic devices, a conducting film, such as, for example,aluminum or tungsten, is deposited over an insulating film and ispatterned by ordinary photolithography and dry etching.

However, in this interconnection forming technique, as devices andinterconnections comprising semiconductor integrated circuit devicesbecome finer, interconnection resistances are largely increasing,interconnection delays are occurring, and a limit is being reached tofurther performance improvements of the semiconductor integrated circuitdevices.

In recent years, an interconnection forming technique known as theDamascene method has been developed. This Damascene method may bebroadly distinguished into two types, i.e., the Single Damascene methodand the Dual Damascene method.

In the Single Damascene method, after forming an interconnection slot inan insulating film, for example, a main conducting layer for forminginterconnections is deposited over this insulating film and in theinterconnection slot, and an embedded interconnection in theinterconnection slot is formed by polishing this main conducting layerby, for example, CMP (Chemical Mechanical Polishing), so that it is leftonly in the interconnection slot.

In the Dual Damascene method, after forming a connecting hole to connectwith the interconnection slot and a substrate interconnection in theinsulating film, a main conducting layer for forming interconnections isdeposited over this insulating film and in the interconnection slot andconnecting hole, and an embedded interconnection in the interconnectionslot and the connecting hole is formed by polishing this main conductinglayer by, for example, CMP (Chemical Mechanical Polishing), so that itis left only in the interconnection slot and connecting hole.

In both methods, a material such as copper or the like is used as thematerial of the main conducting layer of the interconnections from theviewpoint of improving the performance of the semiconductor integratedcircuit device. Copper has the advantage that, compared to aluminum, itsresistance is lower and its permitted current for reliability is morethan two orders of magnitude higher. Hence, the film can be made thinnerto obtain the same interconnection resistance, and the capacitancebetween adjacent interconnections can be reduced.

However, compared to other metals, such as aluminum or tungsten, itdiffuses easily in the insulating film. if copper is used as theinterconnection material, therefore, it is necessary to form a thinconducting barrier film to prevent diffusion of copper on the surface ofthe main conducting layer including copper (bottom surface and sidesurfaces), i.e., on the inner wall surfaces (side surfaces and bottomsurface) of the interconnection slot. There is also a technique toprevent diffusion of copper in the embedded interconnection from theupper surface of the embedded interconnection into the insulating filmby depositing a cap film including, for example, silicon nitride so asto cover the upper surface of the embedded interconnection over theentire surface on the upper surface of the insulating film in which theinterconnection slot is formed.

This kind of embedded interconnection technique is mentioned in, forexample, Japanese Unexamined Patent Publication No. Hei 10(1998)-154709, wherein the embedded properties of a fine contact holewith a high aspect ratio are improved by forming the embeddedinterconnection of high purity copper having an oxygen concentration orsulfur concentration not exceeding 3 ppm, thus enhancing the surfacediffusion properties and fluidity of the copper.

In Japanese Unexamined Patent Publication No. Hei 11(1999)-87349, forexample, a technique is disclosed wherein, after forming theinterconnection slot and connecting hole in the insulating film, acopper film is formed by sputtering using a target having a purity of99.999 wt % (5N) or higher. In this Publication, to facilitate embeddingof the copper, a titanium nitride/titanium film is formed as a barrierlayer over the surface of the interconnection slot and connecting hole.

In Japanese Unexamined Patent Publication No. Hei 11(1999)-87509 orJapanese Unexamined Patent Publication No. Hei 11(1999)-220023, forexample, a technique is disclosed wherein the barrier layer on thebottom surface of a via is removed to lower the resistance of the via.

In Japanese Unexamined Patent Publication No. Hei 11(1999)-16912, forexample, a technique is disclosed wherein the oxide layer formed in theinterconnection part exposed at the bottom of the connecting hole iseliminated by applying heat, plasma or ultraviolet irradiation in areducing atmosphere.

SUMMARY OF THE INVENTION

However, according to tests performed by the Inventors, the followingproblems were found in semiconductor integrated circuit devicetechniques comprising embedded interconnections having copper as themain conducting layer.

Firstly, as the dimensions of the embedded interconnections (linewidths, thicknesses, distances between centers of adjacentinterconnections and intervals between adjacent interconnections) havingcopper as the main conducting layer become finer, the cross-sectionalsurface area of the high resistance conducting barrier film becomelarger relative to the interconnection cross-sectional surface area, andthe resistance of the embedded interconnection is increases. As aresult, there is a limit to performance improvement of the semiconductorintegrated circuit device even though copper is used to enhanceperformance.

Secondly, to resolve the first problem, if the barrier film is simplymade thinner without performing any special treatment or is eliminated,the interconnection resistance can be reduced, but diffusion of copperoccurs and the insulation breakdown resistance between mutually adjacentembedded interconnections falls considerably. As a result, a highreliability semiconductor integrated circuit device cannot be provided.Also, as the yield of the semiconductor integrated circuit device falls,the cost of the semiconductor integrated circuit device increases.

Thirdly, when a silicon nitride film is used as the cap film on theembedded interconnection having copper as the main conducting layer, asilicide substance is formed at the interface of the copper and siliconnitride film, and the resistance of this embedded interconnectionincreases. It was found for the first time by experiments carried out bythe Inventors that diffusion of copper is a major reason for this, aswill be described later. Consequently, there is a limit to improving theperformance of the semiconductor integrated circuit device. There isalso a problem in that the yield and reliability of the semiconductorintegrated circuit device are seriously affected.

Fourthly, peeling occurs between the interconnection layer of theembedded interconnection and the insulating film (e.g., the aforesaidcap layer) formed over the upper layer. As a result, the yield andreliability of the semiconductor integrated circuit device is seriouslyreduced.

It is therefore an object of this invention to provide a technique forreducing the resistance of the embedded interconnection having copper asthe main conducting layer.

It is another object of this invention to provide a technique forimproving the insulation breakdown resistance between embeddedinterconnections having copper as the main conducting layer.

It is another object of this invention to provide a technique forimproving adhesion between the interconnection layer and the cap film ofembedded interconnections having copper as the main conducting layer.

It is another object of this invention to provide a technique forimproving the reliability of an integrated circuit semiconductor devicecomprising embedded interconnections having copper as the mainconducting layer.

It is another object of this invention to provide a technique forimproving the yield of an integrated circuit semiconductor devicecomprising embedded interconnections having copper as the mainconducting layer.

It is another object of this invention to provide a technique forimproving the performance of an integrated circuit semiconductor devicecomprising embedded interconnections having copper as the mainconducting layer.

The above and other objects and novel features of the invention willbecome clear from the following description and the drawings.

The following is a simple description in outline of the aspects andfeatures of the present invention disclosed in this application.

This invention comprises an embedded interconnection having copper as amain component embedded in a depression formed in an insulating film viaa conducting barrier film, and a cap insulating film formed so as tocover the upper surface of the insulating film and embeddedinterconnection layer, the concentration of components other than copperin the embedded interconnection not exceeding 0.8 At. % in the finishedsemiconductor chip.

In accordance with a feature of this invention, as regards the side wallpart of the aforesaid depression, the thickness of the thickest part orthinnest part of the conducting barrier film is less than 10 nm.

In accordance with another feature of this invention, as regards theside wall part of the aforesaid depression, the thickness of thethickest part or thinnest part of the conducting barrier film is notmore than 2 nm.

In accordance with another feature of this invention, the conductingbarrier film in the aforesaid depression does not exist.

In accordance with still another feature of this invention, an embeddedmetal interconnection layer is in direct contact in the aforesaiddepression.

This invention comprises a method including a step of forming adepression in an insulating film formed over a semiconductor substrate,a step of depositing a conducting barrier film over the insulating filmincluding the interior of the depression, a step of depositing a metalfilm having copper as the main component over the conducting barrierfilm including the interior of the depression, and a step of forming anembedded metal interconnection layer via the conducting barrier film inthe interior of the depression by removing the metal film and conductingbarrier film, the concentration of components apart from copper in theembedded metal interconnection layer when the semiconductor chip formedfrom the aforesaid semiconductor substrate is finished, not exceeding0.8 At. %, and the purity of the copper in the metal film when the metalfilm having copper as the principal component is formed, being at least99.999%.

In the aforesaid method of this invention, the aforesaid metal film isformed by a sputtering technique using a target including copper of atleast 99.999% purity.

This method of the present invention, comprises a step wherein, afterremoving the aforesaid metal film by chemical mechanical polishing toform the embedded interconnection, the upper surface of the insulatingfilm and indebted interconnection layer is plasma treated in a gasatmosphere having reducing properties, and a step wherein a capinsulating film is formed over the insulating film and embedded metalinterconnection layer after plasma treatment.

In the method of this invention, the gas atmosphere having reducingproperties has hydrogen as its main component.

In this method, the gas atmosphere having reducing properties also has anitriding action.

In this method, the gas atmosphere having reducing provinces containsammonia as its main component.

In this method, the step of forming the embedded metal interconnectionlayer by removing the metal film is performed by abrasive particle-freechemical mechanical polishing.

In this method, the concentration of components apart from copper doesnot exceed 0.02 At. %.

In this method, the thickness of the thickest part or thinnest part ofthe conducting barrier film in the side wall of the aforesaid depressionis less than 10 nm.

In this method, the thickness of the thickest part or thinnest part ofthe conducting barrier film in the side wall of the aforesaid depressionis not more than 2 nm.

This method further comprises a step wherein, after forming theaforesaid depression, and prior to the step of depositing the conductingbarrier film, the semiconductor substrate is plasma treated in a gasatmosphere having reducing properties.

The method of this invention comprises a step of forming a depression inan insulating film formed over a semiconductor substrate, a step ofdepositing a metal film having copper as the main component over theinsulating film including the interior of the depression without theintervention of a conducting barrier film, and a step of forming anembedded metal interconnection layer in the interior of the depressionwithout the intervention of a conducting barrier film by removing themetal film, the concentration of components apart from copper in theembedded metal interconnection layer, when the semiconductor chip formedfrom the aforesaid semiconductor substrate is finished, not exceeding0.8 At. %, and the purity of the copper in the metal film, when themetal film having copper as the principal component is formed, being atleast 99.999%.

The method of this invention comprises a Damascene interconnectionforming step, comprising a step of forming a depression in an insulatingfilm formed over a semiconductor substrate, a step of depositing aconducting barrier film over the insulating film including the interiorof the depression, a step of depositing a metal film having copper asthe main component over the conducting barrier film including theinterior of the depression, a step of forming an embedded metalinterconnection layer via the conducting barrier film in the interior ofthe depression by removing the metal film and conducting barrier film,and a step of forming a cap insulating film over the insulating film andembedded metal interconnection layer, the concentration of componentsapart from copper in the embedded metal interconnection layer, when thesemiconductor chip formed from the aforesaid semiconductor substrate isfinished, not exceeding 0.8 At. %, and the purity of the copper in themetal film, when the metal film having copper as the principal componentis formed, being at least 99.999%.

The method of this invention comprises a Dual Damascene interconnectionforming step, comprising a step of forming an embedded interconnectionslot and connecting hole in an insulating film formed over asemiconductor substrate, a step of depositing a conducting barrier filmover the insulating film including the embedded interconnection slot andconnecting hole, a step of depositing a metal film having copper as themain component over the conducting barrier film including the embeddedinterconnection slot and connecting hole, a step of forming an embeddedmetal interconnection layer via the conducting barrier film in theembedded interconnection slot and connecting hole by removing the metalfilm and conducting barrier film, and a step of forming a cap insulatingfilm over the insulating film and embedded metal interconnection layer,the concentration of components apart from copper in the embedded metalinterconnection layer, when the semiconductor chip formed from theaforesaid semiconductor substrate is finished, not exceeding 0.8 At. %,and the purity of the copper in the metal film, when the metal filmhaving copper as the principal component is formed, being at least99.999%.

The method of this invention comprises a step wherein, after forming theembedded interconnection slot and connecting hole, the aforesaidsemiconductor substrate is plasma treated in a gas atmosphere havingreducing properties prior to a step of depositing the conducting barrierfilm.

The method of this invention comprises a step wherein, after a step offorming the embedded interconnection layer by removing the metal film bychemical mechanical polishing, the upper surface of the insulating filmand embedded interconnection layer is plasma treated in a gas atmospherehaving reducing properties prior to the step of forming the capinsulating film.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of the essential parts of asemiconductor substrate showing a method of forming a semiconductorintegrated circuit device which represents a first embodiment(Embodiment 1) of this invention.

FIG. 2 is a cross-sectional view of the essential parts of asemiconductor substrate showing a step in the fabrication of Embodiment1.

FIG. 3 is a cross-sectional view of the essential parts of asemiconductor substrate showing a step in the fabrication of Embodiment1.

FIG. 4 is a cross-sectional view of the essential parts of asemiconductor substrate showing a step in the fabrication of Embodiment1.

FIG. 5 is a cross-sectional view of the essential parts of asemiconductor substrate showing a step in the fabrication of Embodiment1.

FIG. 6( a) is a plan view and FIG. 6( b) is a cross-sectional view ofthe essential parts of a semiconductor substrate showing a step in thefabrication of Embodiment 1.

FIG. 7( a) is a plan view and FIG. 7( b) is a cross-sectional view ofthe essential parts of a semiconductor substrate showing a step in thefabrication of Embodiment 1.

FIG. 8 is a cross-sectional view of the essential parts of asemiconductor substrate showing a step in the fabrication method ofEmbodiment 1.

FIG. 9 is a schematic diagram showing an example of the overallconstruction of a CMP apparatus used in forming an embedded Cuinterconnection.

FIG. 10 is a diagram showing part of the construction of a CMP apparatusused in forming an embedded Cu interconnection.

FIG. 11 is a perspective view showing a wafer scrub and rinse method.

FIG. 12 is a schematic diagram showing another example of the overallconstruction of a CMP apparatus used in forming an embedded Cuinterconnection.

FIG. 13 is a schematic diagram showing yet another example of theoverall construction of a CMP apparatus used in forming an embedded Cuinterconnection.

FIG. 14 is a cross-sectional view of the essential part of asemiconductor substrate showing a step in the fabrication of Embodiment1.

FIG. 15( a) is a cross-sectional view showing an outline of a plasmatreatment apparatus used for ammonia plasma treatment and siliconnitride film deposition; and, FIG. 15( b) is a plan view of the same.

FIG. 16 is a cross-sectional view of the essential parts of asemiconductor substrate showing a step in the fabrication of Embodiment1.

FIG. 17 is a cross-sectional view of the essential parts of asemiconductor substrate showing a step in the fabrication of Embodiment1.

FIG. 18 is a flow diagram showing a method of fabricating thesemiconductor integrated circuit device of Embodiment 1.

FIG. 19 is a sectional view showing the essential features of thesemiconductor integrated circuit device of Embodiment 1.

FIG. 20 is a graph showing TDDB life.

FIG. 21 is a graph showing TDDB life.

FIGS. 22( a) to 22(d) are graphs showing XPS data.

FIGS. 23( a) to 23(d) are graphs showing XPS data.

FIGS. 24( a) to 24(d) are graphs showing XPS data.

FIGS. 25( a) to 25(e) are graphs showing XPS data, and FIG. 25( f) is atable showing composition ratios.

FIGS. 26( a) to 26(d) are graphs showing mass analysis results.

FIGS. 27( a) to 27(d) are graphs showing mass analysis results.

FIG. 28 is a graph showing interconnection resistance.

FIG. 29 is a chart showing sectional diagram which trace in part (a) aTEM photograph showing an interconnection part in the case of notreatment, and which trace in part (b) a TEM photograph showing theinterconnection part of Embodiment 1.

FIG. 30 is a chart showing sectional diagrams which trace TEMphotographs for comparison purposes.

FIGS. 31( a) and 31(b) are diagrams showing the mechanism of TDDBdeterioration.

FIGS. 32( a) and 32(b) are diagrams showing the mechanism of TDDBenhancement.

FIG. 33 is a graph showing TDDB life.

FIG. 34 is a schematic diagram showing an example of the overallconstruction of a CMP apparatus used in a method of fabricating asemiconductor integrated circuit device according to Embodiment 2 ofthis invention.

FIG. 35 is a side view showing part of a CMP apparatus used for formingan embedded Cu interconnection.

FIG. 36 is a side view of a CMP apparatus showing the polishing state ofa Cu film.

FIG. 37 is a sectional view of the essential parts of a semiconductorsubstrate showing a step in the method of fabricating the semiconductorintegrated circuit device of Embodiment 2.

FIG. 38( a) is a plan view of the essential parts of a semiconductorsubstrate showing a step in the method of fabricating the semiconductorintegrated circuit device of Embodiment 2, and FIG. 38( b) is asectional view of the essential parts thereof.

FIG. 39 is a sectional view of the essential parts of a semiconductorsubstrate showing a step in the method of fabricating the semiconductorintegrated circuit device of Embodiment 2.

FIG. 40( a) is a plan view of the essential parts of a semiconductorsubstrate showing a step in the method of fabricating the semiconductorintegrated circuit device of Embodiment 2, and FIG. 40( b) is asectional view of the essential parts thereof.

FIG. 41 is a sectional view of the essential parts of a semiconductorsubstrate showing a step in the method of fabricating the semiconductorintegrated circuit device of Embodiment 2.

FIG. 42( a) is a plan view of the essential parts of a semiconductorsubstrate showing a step in the method of fabricating the semiconductorintegrated circuit device of Embodiment 2, and FIG. 42( b) is asectional view of the essential parts thereof.

FIG. 43 is a flowchart showing the method of fabricating thesemiconductor integrated circuit device of Embodiment 2.

FIG. 44 is a graph showing TDDB life.

FIG. 45 is a flowchart showing the method of fabricating thesemiconductor integrated circuit device of Embodiment 3.

FIG. 46 is a graph showing TDDB life.

FIG. 47 is a sectional view of the essential parts of a semiconductorsubstrate showing a step in the method of fabricating the semiconductorintegrated circuit device of Embodiment 4.

FIG. 48( a) is a plan view of the essential parts of a semiconductorsubstrate showing a step in the method of fabricating the semiconductorintegrated circuit device of Embodiment 4, and FIG. 48( b) is asectional view of the essential parts thereof.

FIG. 49 is a sectional view of the essential parts of a semiconductorsubstrate showing a step in the method of fabricating the semiconductorintegrated circuit device of Embodiment 4.

FIG. 50 is a sectional view of the essential parts of a semiconductorsubstrate showing a step in the method of fabricating the semiconductorintegrated circuit device according to another embodiment of thisinvention.

FIG. 51 is a sectional view of the essential parts of a semiconductorsubstrate showing a step in the method of fabricating the semiconductorintegrated circuit device according to another embodiment of thisinvention.

FIG. 52( a) is a plan view of the essential parts of a semiconductorsubstrate showing a step in the method of fabricating the semiconductorintegrated circuit device according to another embodiment, and FIG. 52(b) is a sectional view of the essential parts thereof.

FIG. 53 is a sectional view of the essential parts of a semiconductorsubstrate showing a step in the method of fabricating the semiconductorintegrated circuit device according to another embodiment of thisinvention.

FIG. 54 is a sectional view of the essential parts of a semiconductorsubstrate showing a step in the method of fabricating the semiconductorintegrated circuit device according to another embodiment of thisinvention.

FIG. 55 is a graph showing data which illustrates measure of the TDDBcharacteristics of a copper interconnection, an aluminum interconnectionand a tungsten interconnection.

FIG. 56 is a graph showing the amount of silicon contained in the copperinterconnection when each process is performed.

FIG. 57 is a graph showing conductive barrier film thickness dependencein the resistance of an embedded copper interconnection.

FIG. 58 is a graph showing the conductive barrier film thicknessdependence of TDDB characteristics.

FIG. 59 is a graph showing TDDB characteristics after annealing in thecase when there is no conductive barrier film, and the case of less than10 nm thickness.

FIGS. 60( a) and 60(b) are sectional views of the essential parts of acopper embedded interconnection layer of a semiconductor integratedcircuit device according to another embodiment of this invention.

FIG. 61( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device according to anembodiment of this invention, and FIG. 61( b) is a sectional view takenalong a line A-A in FIG. 61( a).

FIG. 62( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following FIG.61, and FIG. 62( b) is a sectional view taken along a line A-A in FIG.62( a).

FIG. 63( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following FIG.62, and FIG. 63( b) is a sectional view taken along a line A-A in FIG.63( a).

FIG. 64( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following FIG.63, and FIG. 64( b) is a sectional view taken along a line A-A in FIG.64( a).

FIG. 65( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following FIG.64, and FIG. 65( b) is a sectional view taken along a line A-A in FIG.65( a).

FIG. 66( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device according to anembodiment of this invention, and FIG. 66( b) is a sectional view takenalong a line A-A in FIG. 66( a).

FIG. 67( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following thestep in FIG. 66, and FIG. 67( b) is a sectional view taken along a lineA-A in FIG. 6( a).

FIG. 68( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following thestep in FIG. 67, and FIG. 68( b) is a sectional view along line a lineA-A in FIG. 68( a).

FIG. 69( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following thestep in FIG. 68, and FIG. 69( b) is a sectional view taken along lineA-A in FIG. 69( a).

FIG. 70( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following thestep in FIG. 69, and FIG. 70( b) is a sectional view taken along lineA-A in FIG. 70( a).

FIG. 71( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following thestep in FIG. 70, and FIG. 71( b) is a sectional view taken along lineA-A in FIG. 71( a).

FIG. 72( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following thestep in FIG. 71, and FIG. 72( b) is a sectional view taken along lineA-A in FIG. 72( a).

FIG. 73( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following thestep in FIG. 72, and FIG. 73( b) is a sectional view taken along lineA-A in FIG. 73( a).

FIG. 74( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following thestep in FIG. 73, and FIG. 74( b) is a sectional view taken along lineA-A in FIG. 74( a).

FIG. 75( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following thestep in FIG. 74, and FIG. 75( b) is a sectional view taken along lineA-A in FIG. 75( a).

FIG. 76( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following thestep in FIG. 75, and FIG. 76( b) is a sectional view taken along lineA-A in FIG. 76( a).

FIG. 77( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following thestep in FIG. 76, and FIG. 77( b) is a sectional view taken along lineA-A in FIG. 77( a).

FIG. 78( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device according to anembodiment of this invention, and FIG. 78( b) is a sectional view takenalong line A-A in FIG. 78( a).

FIG. 79( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following thestep in FIG. 78, and FIG. 79( b) is a sectional view taken along lineA-A in FIG. 79( a).

FIGS. 80( a) and 80(b) are sectional views of the essential parts of acopper embedded interconnection layer of a semiconductor integratedcircuit device according to yet another embodiment of this invention.

FIG. 81( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device according to anembodiment of this invention, and FIG. 81( b) is a sectional view takenalong line A-A in FIG. 81( a).

FIG. 82( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following thestep in FIG. 81, and FIG. 82( b) is a sectional view taken along lineA-A in FIG. 82( a).

FIG. 83( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following thestep in FIG. 82, and FIG. 83( b) is a sectional view taken along lineA-A in FIG. 83( a).

FIG. 84( a) is a plan view of the essential parts in a process formanufacturing a semiconductor integrated circuit device following thestep in FIG. 83, and FIG. 84( b) is a sectional view taken along lineA-A in FIG. 84( a).

FIGS. 85( a) to 85(c) are diagrams which show samples used for TDDB lifemeasurement, in which FIG. 85( a) is a plan view, and FIG. 85( b) andFIG. 85( c) are cross-sectional diagrams respectively showing a sectiontaken along line B-B′ and a section taken along line C-C′ in FIG. 85(a).

FIG. 86 is a diagram showing the essential features of the measurement.

FIG. 87 is a graph of current-voltage measurement results.

FIG. 88 is a diagram showing the coverage in an interconnection slot orconnecting hole of a conductive barrier film.

DETAILED DESCRIPTION OF THE INVENTION

In describing the embodiments of this invention, the basic meaning ofthe terminology used in this application is as follows.

1. TDDB (Time Dependence on Dielectric Breakdown) life means a timecalculated by applying a comparatively high voltage between electrodesunder measurement conditions at a predetermined temperature (forexample, 140° C.), plotting a graph of the time from applying thevoltage to insulation breakdown relative to the applied electric field,and extrapolating to the actual field intensity used (for example, 0.2MVP/cm). FIG. 85( a) shows a sample used for the TDDB life measurement.FIG. 85( a) is a plan view, and FIG. 85( b) and FIG. 85( c) respectivelyshow a section taken along line B-B′ and a section taken along line C-C′in FIG. 85( a). This sample can be formed in the TEE (Test EquipmentGroup) region of a semiconductor wafer. A pair of comb-shapedinterconnections L are formed in a second interconnection layer M2, asshown in the diagram, and the interconnections L are respectivelyconnected to pads P1, P2 of an uppermost layer. An electric field isapplied between these comb-shaped interconnections L, and the electriccurrent is measured. The pads P1, P2 are measurement terminals.

The line widths, line intervals and line thicknesses of the comb-shapedinterconnections L are all 0.5 μm. The interconnection facing lengthswere 1.58×10⁵ μm. FIG. 86 is a conceptual diagram showing the essentialfeatures of the measurement. The sample is held on a measurement stageS, and a current-voltage measuring instrument (I/V meter) is connectedbetween the pads P1, P2. The sample stage S is heated by a heater H, andthe sample temperature is adjusted to 140° C. FIG. 87 is a graph showingan example of current-voltage measurement results. The case using a 140°C. sample temperature and a field intensity of 5 MVP/cm was taken as anexample. The constant voltage stress method or the low current stressmethod may be used for the TDDB life measurement, but in thisapplication, the constant voltage stress method wherein the averageelectric field applied to an insulating film is fixed, is used. Afterapplying the voltage, the current density decreases with time, and arapid increase in current (insulation breakdown) is observed thereafter.Here, the time when the leakage current density reached 1 μA/cm² wastaken as the TDDB life (TDDB life at 5 MVP/cm).

In this application, although the term TDDB life means the breakdowntime (life) at 0.2 MVP/cm unless otherwise specified, the term TDDB lifemay be used in a wider sense as the time until breakdown if apredetermined field intensity is specified.

Unless otherwise specified, TDDB life refers to the case where thesample temperature is 140° C. Further, TDDB life refers to measurementsperformed on the above-mentioned comb-shaped interconnection L, but itwill be understood to reflect the breakdown life between actualinterconnections.

2. Plasma treatment refers to a process wherein, when a member, such asan insulating film and a metal film, are formed over a substrate surfaceor over a substrate in a plasma state, the surface of the member isexposed, and the surface is subjected to the chemical and mechanical(bombardment) action of the plasma.

Although plasma is usually generated by filling a reaction chamber, inwhich the atmosphere has been replaced by a specific gas (treatmentgas), with more treatment gas, and ionizing the gas by the action of ahigh frequency field etc., the gas in the chamber cannot be completelyreplaced by the treatment gas. Therefore, in this application, althoughreference is made to an ammonia plasma, for example, a perfect ammoniaplasma is not meant, and the possible presence of impurity gases(nitrogen, oxygen, carbon dioxide, steam, etc.) in the plasma cannot bediscarded. Likewise, this does not exclude the possibility that otherdiluting gases and added gases are contained in the plasma.

A plasma of a reducing atmosphere means a plasma environment whereinreactive species, such as radicals, ions, atoms and molecules which havea reducing action, i.e., an action which withdraws oxygen, existdominantly, atomic or molecular radicals or ions being included in saidradicals and ions.

Moreover, in such an environment, not only a single reactive species,but two or more reactive species may be included. For example, anenvironment where hydrogen radicals and NH2 radicals existsimultaneously may be sufficient.

3. In this application, gas concentration shall refer to flow rate ratioin mass flow rates. That is, in a mixture of Gas A and Gas B, when theconcentration of Gas A is 5%, it means Fa/(Fa+Fb)=0.05 where the massflow rate of Gas A is Fa and the mass flow rate of Gas B is Fb.

4. Chemical mechanical polishing (CMP) usually means a process where asurface to be polished is brought in contact with a polishing padcomprising a sheet of relatively soft cloth, etc., and polishing isperformed by making a relative movement in the direction of the surfacewhile a slurry is supplied. This application shall also be understood torefer to a CML (Chemical Mechanical Lapping) where the surface to bepolished is moved relative to a hard abrasive stone, the use of otherfixed abrasive particles, and abrasive particle-free CMP which does notuse abrasive particles.

Abrasive particle-free chemical mechanical polishing usually meanschemical mechanical polishing with a slurry having a weightconcentration of abrasive particles of 0.5% or less, and abrasiveparticle polishing means chemical mechanical polishing using a slurryhaving a higher concentration of abrasive particles than a weightconcentration of 0.5%. However, these are relative terms, and when thepolishing of the first step is an abrasive particle-free chemicalmechanical polishing and the polishing of the following second step isan abrasive particle polishing, or the polishing concentration of thefirst step is smaller than the polishing concentration of the secondstep by one or more orders of magnitude, and preferably two or moreorders of magnitude, the polishing of the first step may be referred toas abrasive particle-free chemical mechanical polishing. In thisSpecification, when using the term abrasive particle-free chemicalmechanical polishing, it shall be understood to include not only thecase where the whole planarizing process of the target metal film isperformed by abrasive particle-free chemical mechanical polishing, butalso the case where the main process is performed by abrasiveparticle-free chemical mechanical polishing and the secondary process isperformed by abrasive particle polishing.

5. Polishing liquid (slurry) generally means a suspension in whichpolishing abrasive particles are mixed with chemical etching reagents,and in the context of this application, due to the nature of theInvention, it shall be understood to include the case where polishingabrasive particles are not mixed with the reagents.

Moreover, abrasive particles (slurry particles) means a powder such asis usually included in a slurry (alumina, silica).

6. Anticorrosives mean reagents which prevent or suppress polishing byCMP, by forming a protective film which has the property of corrosionresistance or hydrophobicity, or both, on the surface of a metal,benzotriazole (BTA) or the like usually being employed for this purpose(see Japanese Unexamined Patent Publication No. Hei 8 (1996)-64594.

7. Conductive barrier film is an electrically conducting film having adiffusion barrier property formed in the side face or the bottom surfaceof an embedded interconnection comparatively thinly in order to preventcopper from diffusing into an interlayer insulating film, or a lowerlayer, and in general, high melting point metals or their nitrides, suchas titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN), areused.

8. An embedded interconnection or an embedded metal-interconnectiongenerally means an interconnection which is patterned by aninterconnection forming technique wherein a conducting film is embeddedin slot formed in an insulating film, and unnecessary conducting film onthe insulating film is removed, such as Single Damascene or DualDamascene. Single Damascene is generally an embedded interconnectionprocess wherein a plug metal and an interconnection metal are embeddedin two stages. Likewise, Dual Damascene is generally an embeddedinterconnection process wherein the plug metal and interconnection metalare embedded in one operation. In general, copper embeddedinterconnections are often used in multilayer compositions.

9. When referring to selective removal, selective polishing, selectiveetching and selective chemical mechanical polishing, the selection ratioin all cases is 5 or more.

10. When it is said that the selection ratio of A to B (or B withrespect to A) is X, it means that, taking the polishing rate as anexample, the polishing rate of A, calculated based on the polishing rateof B, is X.

11. The expression semiconductor integrated circuit device in thisapplication refers not only to devices formed on single crystal siliconsubstrates, but also those formed on other substrates such, as a SiliconOn Insulator substrate or a TFT (Thin Film Transistor) liquid crystalsubstrate, except when otherwise specified. Moreover, wafer means asingle crystal silicon substrate (in general, substantiallydisk-shaped), SOS substrate, glass substrate, other insulating,half-insulating or semiconductor substrates, or compounds of same, usedin the fabrication of semiconductor integrated circuit devices.

12. The expression semiconductor integrated circuit wafer (semiconductorintegrated circuit substrate) or semiconductor wafer (semiconductorsubstrate) means silicon or other single crystal substrates (in general,substantially disk-shaped), sapphire substrate, glass substrate, otherinsulating, semi-insulating or semiconductor substrates, orcompound-type substrates, used in the fabrication of semiconductorintegrated circuit devices. In addition, part or all of the substratesurface, or part or all of the gate electrode, may be formed of othersemiconductors, for example, SiGe.

A semiconductor integrated circuit chip (semiconductor integratedcircuit substrate) or a semiconductor chip (semiconductor substrate)means a semiconductor wafer finished in a wafer step divided into groupsof individual circuits.

13. The expression silicon nitride, or a silicon nitride film, includesnot only S′3N, but also insulating films which are silicon nitrides ofsimilar composition.

14. A cap film is an insulating film having high insulating propertiesand high diffusion barrier properties formed in addition to anelectrical connecting part of the information of an embeddedinterconnection, and is generally formed of a material different fromthe main part of the interlayer insulating film, for example, a siliconnitride film.

15. The term wafer process is also known as a preliminary process, andis a process wherein, starting from a mirror wafer, a device and aninterconnection forming step is performed, a surface protecting film isformed, and electrical tests are then performed by a probe.

16. The coverage in the interconnection slot (depression) or conductinghole (depression) of the conducting barrier film comprises side coverageand bottom coverage. FIG. 88 schematically shows the upper surface of aninsulating film 60, and a state where a barrier film 62 is deposited bysputtering in an interconnection slot 61 formed in the insulating film60. The deposited film thickness of the barrier film generally refers toa film thickness D1 of the barrier film 62 on the upper surface of theinsulating film 60. Side coverage means the amount of covering of thebarrier film 62 in a side wall part in the interconnection slot 61(including the angle part in the intersection of the side and bottom),and the film thickness D2 in this part is the thinnest. Bottom coveragemeans the amount of covering of the barrier film 62 on the bottomsurface in the interconnection slot 61, and the film thickness D3 inthis part is the next thickest after the aforesaid deposited filmthickness. For example, according to experimental results obtained bythe Inventors, when a barrier film was deposited in an interconnectionslot having an aspect ratio of 1 in the usual sputtering method, whichdoes not take directivity into particular consideration, the depositedfilm thickness of the barrier film was 100 nm, the side coverage wasabout 30 nm and the bottom coverage was about 50 nm. Moreover, when thebarrier film was deposited by the long throw sputtering technique, thedeposited film thickness of the barrier film was 100 nm, the sidecoverage was about 20 nm and the bottom coverage was about 90 nm.

17. Long throw sputtering means a sputtering method in which there is animprovement in bottom coverage, wherein the distance between target andsubstrate is increased, and stable discharge at a low voltage isperformed in order to make only the perpendicular component of thesputtering particles reach the substrate.

18. Collimate sputtering is a technique having a mechanism wherein, whena film is formed in a depression such as an interconnection slot orconnecting hole having a large aspect ratio, in order to obtainsufficient film thickness up to the base, a lattice plate isintercalated between the target and substrate to forcibly increase theperpendicular component.

The following embodiments are divided into plural sections orembodiments when required for convenience of description, but unlessotherwise stated, they are not unrelated to each other, one part beingrelated to part or all of the others by way of modifications, detailsand supplementary description.

Moreover, in the following embodiments, when the number of components ismentioned (including numbers, numerical values, amounts, ranges, etc.),the invention is not limited to these specific numbers, except whenotherwise specified or when it is clearly limited to these specificnumbers, and it may pertain to numbers which are higher or lower thanthese specific numbers.

Further, in the following embodiments, it will be understood that theinvention is not necessarily limited to the described component elements(including component steps), except when otherwise specified or whenthey are clearly indispensable.

Likewise, in the following embodiments, when referring to shapes andpositional relationships of component elements, they shall be understoodto include substantially approximate or similar shapes, except whenotherwise specified or when this is clearly not the case. This alsoapplies to the above-mentioned numerical values and ranges.

In all the diagrams used for describing the embodiments, elements havingidentical functions are assigned the same symbols, and their descriptionis not repeated.

Moreover, in this embodiment, a Metal Insulator Field Effect Transistorwhich is representative of field effect transistors is abbreviated toMIS, p channel MISFET is abbreviated to PMIS, and n channel MISFET isabbreviated to NMIS.

EMBODIMENT 1

In this embodiment 1, the application of this invention to a method offabricating a CMOS (Complementary MOS)-LSI (Large Scale IntegratedCircuit), for example, will be described in a sequence of steps withreference to FIG. 1-FIG. 19.

First, as shown in FIG. 1 for example, after forming a device isolationslot 2 to a depth of about 350 nm in a semiconductor substrate(henceforth substrate) 1 comprising p type single crystal silicon havinga resistivity of about 1-10 Ωcm by photolithography and dry etching, asilicon oxide film 3 is deposited by the CVD method over the substrate 1including the interior of the slot. The surface of the silicon oxidefilm 3 overlying the slot is then planarized by chemical mechanicalpolishing (CMP). This forms a slot type isolation part 2A (trenchisolation). Subsequently, after forming a p type well 4 and a n typewell 5 by carrying out ion implantation of a p type impurity (boron) anda n type impurity (for example, phosphorus) to the substrate 1, a gateinsulation film 6 of about 6 nm film thickness is formed over thesurface of the p type well 4 and n type well 5 by steam oxidation of thesubstrate 1. The film thickness of the gate insulation film 6 here is asilicon dioxide equivalent film thickness, and it may not be inagreement with the actual film thickness.

The gate insulation film 6 may comprise a silicon oxide/nitride filminstead of a silicon oxide film. A silicon oxide/nitride film is moreeffective than a silicon oxide film in suppressing the generation ofinterface levels in the film, or reducing electron traps, so a siliconoxide/nitride film can improve the hot carrier resistance of the gateinsulation film 6, and can improve its dielectric strength. To form asilicon oxide/nitride film, it is sufficient, for example, to heat thesubstrate 1 in a nitrogen-containing gas atmosphere, such as NO, NO₂ orNH₃. The same effect is achieved by forming the gate insulation film 6including silicon oxide in the surface of each of the p type well 4 andn type well 5, heat-treating the substrate 1 in the aforesaidnitrogen-containing gas atmospheres, and segregating nitrogen at theinterface of the gate insulation film 6 and substrate 1.

The gate insulation film 6 may also be formed of, for example, a siliconnitride film, or a compound film comprising a silicon oxide film and asilicon nitride film. If the gate insulation film 6 comprising siliconoxide is made less than 5 nm, and, more particularly, less than 3 nm interms of silicon dioxide equivalent film thickness, the decrease ofinsulation breakdown voltage is remarkable due to generation of a directtunnel current or hot carriers due to stress. Since the dielectricconstant of the silicon nitride film is higher than that of a siliconoxide film, its silicon dioxide equivalent film thickness is thinnerthan its real film thickness.

That is, even when a silicon nitride film is provided and it isphysically thick, approximately the same capacitance as that of arelatively thin silicon dioxide film can be obtained. Therefore, byforming the gate insulation film 6 from a single silicon nitride film ora compound film of this and silicon oxide, the effective film thicknesscan be made thicker than that of a gate insulation film 6 comprising asilicon oxide film, so a decrease of the insulation breakdown voltagedue to generation of tunnel leakage current or hot carriers can besuppressed. Further, it is more difficult for impurities to penetrate asilicon oxide/nitride film than a silicon oxide film; therefore, byforming the gate insulation film 6 from a silicon oxide/nitride film,the fluctuation of threshold voltage resulting from diffusion ofimpurities of the gate electrode material into the semiconductorsubstrate can be suppressed.

If the specific inductive capacitance of an insulating film is εi, itsfilm thickness is di and the specific inductive capacitance of siliconoxide is εS, the silicon dioxide equivalent film thickness (hereafter,referred to also as equivalent film thickness) of a single insulatingfilm or a compound insulation film dr is a film thickness defined by thefollowing equation.

$\begin{matrix}{{dr} = {\sum{\frac{ɛ\; i}{ɛ\; s}{di}}}} & \left\lbrack {{Equation}\mspace{14mu} 1} \right\rbrack\end{matrix}$

For example, the dielectric constants of silicon oxide (SiO₂) andsilicon nitride (Si₃N₄) are respectively 4-4.2 and 8. Then, if thedielectric constant of silicon nitride is calculated as twice thedielectric constant of silicon oxide, the silicon dioxide equivalentfilm thickness of a silicon nitride film of 6 nm film thickness, forexample, will be 3 nm. That is, a gate insulation film comprising asilicon nitride film of 6 nm film thickness, and a gate insulation filmcomprising a silicon oxide film of 3 nm film thickness, have equalcapacitance. Moreover, the capacitance of a gate insulation filmcomprising a compound film comprising a silicon oxide film of 2 nm filmthickness and a silicon nitride film of 2 nm film thickness (convertedfilm thickness=1 nm), is the same as the capacitance of a gateinsulation film comprising a single silicon oxide film of 3 nm filmthickness.

Next, as shown in FIG. 2, a gate electrode 7 comprising a low resistancepolycrystalline silicon film, WN (tungsten nitride) film, and W(tungsten) film is formed over the upper part of the gate insulationfilm 6. The polycrystalline silicon film can be formed by CVD, and theWN film and W film can be formed by sputtering. The gate electrode 7 isformed by the patterning of these deposited films. The gate electrode 7may be formed using a deposited film wherein a W silicide film or cobalt(Co) silicide film is deposited over a low resistance polycrystallinesilicon film. The material of the gate electrode 7 may also be an alloyof polycrystalline or single crystal silicon (Si) and germanium (Ge).After forming such a gate electrode 7, a n⁻ semiconductor region 11 oflow impurity concentration is formed in the p type well 4, and a p⁻semiconductor region 12 of low impurity concentration is formed in the ntype well 5 by ion implantation.

Next, as shown in FIG. 3, a silicon nitride film is deposited by CVD forexample, and a side wall spacer 13 is formed in the side wall of thegate electrode 7 by anisotropic etching. Subsequently, a n⁺semiconductor region 14 (source, drain) of high impurity concentrationis formed in the p type well 4, and a p⁺ semiconductor region 15(source, drain) of high impurity concentration is formed in the n well 5by ion implantation. The n type impurity is typically phosphorus orarsenic, and the p type impurity is typically boron. Subsequently, metalfilms such as titanium and cobalt are deposited, and silicide layers 9are formed in the surface of the n⁺ semiconductor region 14 (source,drain) and the surface of the p⁺ semiconductor region 15 (source, drain)using the so-called salicide method which removes unreacted metal filmafter heat treatment. The performing of the above steps completes thefabrication of a n channel MISFETQn and p channel MISFETQp.

Next, as shown in FIG. 4, a silicon oxide film 18 is deposited over thesubstrate 1 by CVD, and by dry etching the silicon oxide film 18 using aphotoresist film as a mask, a contact hole 20 is formed over the n⁺semiconductor region 14 (source, drain), and a contact hole 21 is formedover the p⁺ semiconductor region 15 (source, drain). A contact hole 22is formed also over the gate electrode 7 at this time.

The silicon oxide film 18 comprises a film with high reflow propertieswhich can be embedded in the narrow space between the gate electrodes 7,7, for example, a BPSG (Boron-doped Phospho Silicate Glass) film. A SOG(Spin On Glass) film formed by the spin coating method may also be used.

Next, a plug 23 is formed inside the contact holes 20, 21 and 22. Toform the plug 23, for example, a TiN film and a W film are deposited byCVD over the upper part of the silicon oxide film 18 including theinside of the contact holes 20, 21 and 22. Unnecessary TiN film andunnecessary W film over the upper part of the silicon oxide film 18 areremoved by chemical mechanical polishing (CMP) or the etch back method,leaving these films only on the insides of the contact holes 20, 21 and22.

Next, as shown in FIG. 5, W interconnections 24 to 30 which form a firstinterconnection layer are formed over the silicon oxide film 18. To formthe W interconnections 24 to 30, a W film is for example deposited overthe upper part of the silicon oxide film 18 by sputtering, and the Wfilm is dry etched using a photoresist film as a mask. The first layerof W interconnections 24 to 30 are electrically connected with thesource and drain of the n channel MISFETQn (n⁺ semiconductor region),source and drain of the p channel MISFETQp (p⁺ semiconductor region), orthe gate electrode 7 through the contact holes 20, 21 and 22.

Next, as shown in FIGS. 6( a) and 6(b), after depositing the siliconoxide film 31 over the first layer of W interconnections 24 to 30, andforming through holes 32 to 36 in the silicon oxide film 31 by dryetching using a photoresist film as a mask, a plug 37 is formed in thethrough holes 32 to 36. FIG. 6( a) is a plan view of the essential partsof the main surface of the semiconductor substrate, and FIG. 6( b) is asectional view taken along a line A-A in FIG. 6( a).

The silicon oxide film 31 is deposited by plasma CVD using for exampleozone (or oxygen) and tetraethoxysilane (TEOS) as the source gas. Theplug 37 may also comprise a W film, and is formed by the same method asused for the aforesaid plug 23 formed inside the contact holes 20, 21and 22.

Next, as shown in FIGS. 7( a) and 7(b), a thin silicon-nitride film 38of 50 nm film thickness is deposited by plasma CVD over the upper partof the silicon oxide film 31, and a silicon oxide film 39 of about 450nm film thickness is then deposited by plasma CVD over the upper part ofthe silicon nitride film 38. Subsequently, the silicon oxide film 39 andsilicon nitride film 38 overlying the through holes 32 to 36 are removedby dry etching using a photoresist film as a mask so as to forminterconnection slots 40 to 44. FIG. 7( a) is a plan view of theessential parts of the main surface of the semiconductor substrate, andFIG. 7( b) is a sectional view taken along line A-A in FIG. 7( a).

To form the interconnection slots 40 to 44, the silicon oxide film 39 isfirst selectively etched using the silicon nitride film 38 as an etchingstopper, and then the silicon nitride film 38 is etched. By forming thethin silicon nitride film 38 underneath the silicon oxide film 39 inwhich the interconnection slots 40 to 44 are formed, temporarilystopping the etching at the surface of this silicon nitride film 38 andthen etching the silicon nitride film 38, the depth can be controlledwith high precision without producing over-etching of theinterconnection slots 40 to 44.

Next, the embedded Cu interconnection, which is the secondinterconnection layer, is formed by the following method inside theinterconnection slots 40 to 44.

First, as shown in FIG. 8, after depositing a thin TiN (titaniumnitride) film 45 over the upper part of the silicon oxide film 39including the inside of the interconnection slots 40 to 44 bysputtering, a Cu film 46 of a film thickness sufficiently larger thanthe depth of the interconnection slots 40 to 44 (for example, about 800nm) is deposited over the upper part of the TiN film 45 by sputtering.For the sputtering of this TiN film 45 and Cu film 46, the usualsputtering methods may be used, and highly directional sputteringmethods, such as long throw sputtering and collimate sputtering, mayalso be used.

Then, by heat-treating the substrate 1, for example in a non-oxidizingatmosphere (for example, a hydrogen atmosphere) at about 475° C., reflowof the Cu film 46 is performed to embed the Cu film 46 inside theinterconnection slots 40 to 44 without any gaps. Herein, the Cu film 46was formed by sputtering and then embedded by reflow, but instead a thinCu film may be formed by sputtering, and a Cu film of high puritycorresponding to the Cu film 46 subsequently formed by plating.

The TiN film 45 has the function of preventing diffusion of Cu. The TiNfilm 45 also has the function of improving the adhesive properties ofthe Cu film 46 and silicon oxide film 39. The TiN film 45 further hasthe function of increasing the wettability of the Cu film 46 at the timeof reflow of the Cu film 46.

In this Embodiment 1, although a case has been described where thethickness of the thickest part of the TiN film 45 was 50 nm, accordingto results obtained by the Inventors, it is clear that this TiN film 45can be made still thinner or eliminated. This will be described laterwith reference to Embodiment 6 and subsequent embodiments.

It is preferable to use high melting point metal nitrides which hardlyreact with Cu, such as WN, and TaN (tantalum nitride), instead of TiN asthe film having such functions. Moreover, materials wherein Si is addedto high melting point metal nitrides or high melting point metals suchas Ta, Ti, W or TiW alloy which cannot react easily with Cu, can also beused instead of TiN.

Next, the Cu film 46 and TiN film 45 are polished by the above CMPmethod. An example of the overall construction of the CMP apparatus usedfor this polishing step is shown in FIG. 9.

This CMP apparatus 100 is a single wafer treatment CMP apparatus usedfor polishing the Cu film 46. It comprises a loader 120, whichaccommodates plural substrates 1 having the Cu film 46 formed in thesurface; a polishing treatment part 130 which polishes and planarizesthe Cu film 46; an anticorrosion treatment part 140, which appliesanticorrosion treatment to the surface of the substrate 1 that hasreceived polishing treatment; an immersion part 150, which ensures thatthe surface does not dry until the substrate 1, which has receivedanticorrosion treatment, is subjected to post-washing; a post-washingpart 160, which post-washes the substrate 1 which has receivedanticorrosion treatment; and an unloader 170, which accommodates pluralsubstrates 1 that have been subjected to post-washing.

As shown in FIG. 10, the polishing treatment part 130 of the CMPapparatus 100 comprises a frame 101 of which the upper part is open, anda polishing plate (platen) 104 driven by a motor 103 is attached to theupper end of a rotation shaft 102 that is attached to this frame 101. Apolishing pad 105, which is formed by uniformly attaching a syntheticresin having plural pores, is attached to the surface of this polishingplate 104.

This polishing treatment part 130 is equipped with a wafer carrier 106for retaining the substrate 1. A drive shaft 107, to which the wafercarrier 106 is attached, is driven by a motor, not shown, together withthe wafer carrier 106, and moves up and down above the polishing plate104.

The substrate 1 is retained in the wafer carrier 106, with its mainsurface, i.e., polished surface, facing down, by a vacuum adsorptionmechanism, not shown, provided in the wafer carrier 106. A depression106 a, in which the substrate 1 is accommodated, is formed at the lowerend of the wafer carrier 106; and, when the substrate 1 is accommodatedin this depression 106 a, the surface to be polished is almost flushwith or slightly protrudes from the underside surface of the wafercarrier 106.

A slurry supply pipe 108 for supplying a polishing slurry (S) betweenthe surface of the polishing pad 105 and the surface of the substrate 1to be polished, is provided above the polishing plate 104, and thesurface of the substrate 1 to be polished is polished chemically andmechanically by the polishing slurry (S) supplied from its lower end.The main components of the polishing slurry (S) are abrasive particles,such as alumina, and oxidizing agents, such as hydrogen peroxide wateror aqueous ferrous nitrate solution, these being dispersed or dissolvedin water.

The polishing treatment part 130 comprises a dresser 109, which is atool for dressing the surface of the polishing pad. This dresser isattached to the lower end of a drive shaft 110 which moves up and downabove the polishing plate 104 and is driven in rotation by a motor, notshown.

In the anticorrosion treatment part 140, the surface of the substrate 1,which has received polishing treatment, then receives anticorrosiontreatment. The anticorrosion treatment part 140 has a constructionsimilar to that of the polishing treatment part 130. Here, after themain surface of the substrate 1 is pushed against the polishing padattached to the surface of the polishing plate (platen) to remove thepolishing slurry mechanically, a hydrophobic protective film is formedin the surface part of the Cu interconnection formed over the mainsurface of the substrate 1 by supplying a chemical solution containingan anticorrosion agent, such as benzotriazole (BTA), to the main surfaceof the substrate 1.

In mechanical cleaning (pre-washing) of the polishing slurry, as shownfor example in FIG. 11, both sides of the substrate 1, rotated in ahorizontal plane, are gripped by cylindrical brushes 121A, 121Bcomprising a porous body of a synthetic resin, such as PVA (polyvinylalcohol), and both surfaces of the substrate 1 are simultaneously washedwhile the brushes 121A, 121B are rotated in a plane perpendicular to thesurface of the substrate 1. In the anticorrosion treatment afterpre-washing, by performing a pure water scrub wash, pure waterultrasonic cleaning, pure water cleaning with running water or purewater spin washing prior to or at the same time as anticorrosiontreatment, the oxidizing agent in the polishing slurry which adhered tothe main surface of the substrate 1 in the polishing treatment part 130is completely removed, and the hydrophobic protective film is formedunder conditions in which the oxidizing agent has no substantial effect.

The substrate 1 which has received anticorrosion treatment istemporarily held by the immersion treatment part 150 in order to preventdryness of the surface. The immersion treatment part 150 is intended tostop the surface of the substrate 1 which has received anticorrosiontreatment from drying until the post-washing stage, and it has aconstruction in which, for example, a predetermined plural number of thesubstrates 1 are immersed in an immersion tank (stocker) overflowingwith pure water. At this time, the corrosion of the Cu interconnections28 to 30 can be further definitively prevented by supplying pure water,cooled to a low temperature at which the electrochemical corrosionreaction of the Cu interconnections 28 to 30 does not proceed to anygreat extent, to the immersion tank.

The dryness of the substrate 1 may be prevented by methods other thanstorage in the above-mentioned immersion tank, such as, for example, apure water shower, provided that the surface of the substrate 1 can atleast be maintained in the wet state.

The substrate 1 transported to the post-washing treatment part 160 isimmediately given a post-washing, where the wet state of the surface ismaintained. Here, after scrub washing (or brush washing) the surface ofthe substrate 1, while supplying weak alkaline chemical solutions, suchas a washing liquid containing NH40H, to neutralize the oxidizing agent,an aqueous hydrofluoric acid solution is supplied to the surface of thesubstrate 1 to remove foreign matter (particles) by etching. Also, thesurface of the substrate 1 may be subjected to a pure water scrub wash,pure water ultrasonic cleaning, pure water cleaning with running wateror a pure water spin wash, and the undersurface of the substrate 1subjected to a pure water scrub wash, prior to or at the same time asthe aforesaid scrub wash.

After a pure water rinse and spin drying, the substrate 1 which hasreceived the post-washing is accommodated in the unloader 170 in the drystate and is transported in plural units to the following step.

In addition, the immersion treatment part (wafer storage part) 150 forpreventing surface dryness of the substrate 1, which has receivedanticorrosion treatment, may be given a shielded structure so that thesurface of the substrate 1 under storage can be prevented from beingirradiated by lighting, as shown in FIG. 12. This can prevent generationof short-circuit currents by the photovoltaic effect. When the immersiontreatment part 150 is given a shielded structure, the area around theimmersion tank (stocker) is covered with a shield, etc., so that theilluminance inside the immersion tank (stocker) does not exceed 500 lux,preferably does not exceed 300 lux, and more preferably does not exceed100 lux.

As shown in FIG. 13, immediately after polishing, i.e., before theelectrochemical corrosion reaction by the oxidizing agent in thepolishing slurry remaining on the surface starts, the substrate 1 may beimmediately transported to the drying treatment part, and the moisturein the polishing slurry removed by forced drying. The CMP apparatus 200shown in FIG. 13 comprises a loader 220, which accommodates pluralsubstrates 1 having a Cu film formed over the surface; a polishingtreatment part 230, which polishes and planarizes the Cu film and formsinterconnections; a drying treatment part 240, which dries the surfaceof the substrate 1 that has received polishing treatment; a post-washingtreatment part 250, which carries out post-washing of the substrate 1;and an unloader 260, which accommodates plural substrates 1 that havereceived post-washing. In the Cu interconnection forming process usingthis CMP apparatus 200, the substrate 1 subjected to polishing treatmentin the polishing treatment part 230 is transported to the dryingtreatment part 240 immediately after the polishing treatment, i.e.,before the electrochemical corrosion reaction due to the oxidizing agentin the polishing slurry remaining on the surface starts, and themoisture in the polishing slurry is removed by forced drying. Then, thesubstrate 1 is transported to the post-washing treatment part 250 whilethe dry state is maintained, and after it is given a post-washingtreatment, it is accommodated in the unloader 260 after a pure waterrinse and spin drying. In this case, since the surface of the substrate1 is maintained in the dry state immediately, after polishing treatmentuntil post-washing is started, the start of the electrochemicalcorrosion reaction is suppressed, and corrosion of the Cuinterconnections can thus be effectively prevented.

After the polishing step in this CMP method, the Cu film 46 and TiN film45 over the silicon oxide film 39 are removed, and, as shown in FIG. 14,Cu interconnections 46 a to 46 e are formed in the interconnection slots40 to 44.

Next, plasma treatment is given to the surface of the Cuinterconnections 46 a to 46 e and silicon oxide film 39. FIG. 15( a) isa sectional view and FIG. 15( b) is a plan view showing an example ofthe apparatus used for plasma treatment. This plasma treatment isdisclosed by Japanese Unexamined Patent Publication No. Hei11(1999)-226876 submitted by the Inventors.

In this treatment apparatus, two treatment chambers 302 a, 302 b and acassette interface 303 are attached to a load lock chamber 301. A robot304 which transports the substrate 1 is provided in the load lockchamber 301. A gate valve 305 is provided between the load lock chamber301 and treatment chambers 302 a, 302 b, so that the high vacuum stateof the load lock chamber 301 can be maintained.

A susceptor 306 which holds the substrate 1, a baffle plate 307 whichadjusts the gas flow, a supporting member 308 which supports thesusceptor 306, a mesh-shaped electrode 309 disposed facing the susceptor306 and an insulating plate 310 disposed substantially opposite thebaffle plate 307, are arranged in the treatment chambers 302 a, 302 b.The insulating plate 310 has an action which suppresses parasiticdischarges in unnecessary regions other than between the susceptor 306and electrode 309. A lamp 312 is installed in a reflective unit 311,arranged on the rear side of the susceptor 306, and infrared rays 313emitted by the lamp 312 pass through a quartz aperture 314 to irradiatethe susceptor 306 and substrate 1. Thereby, the substrate 1 is heated.The substrate 1 is installed face up on the susceptor 306.

The interior of the treatment chambers 302 a, 302 b can be evacuated toa high vacuum, and treatment gas together with high frequency power issupplied from a gas port 315. The treatment gas is supplied to thevicinity of the substrate 1 via the mesh-shaped electrode 309. Thetreatment gas is evacuated from a vacuum manifold 316, and the pressureis controlled by controlling the supply flow rate and discharge rate oftreatment gas. The high frequency power is applied to the electrode 309,and it generates a plasma between the susceptor 306 and electrode 309.The high frequency power uses, for example, a frequency of 13.56 MHz.

In the treatment chamber 302 a, the ammonia plasma treatment to bedescribed below is performed, for example. In the treatment chamber 302b, a cap film (silicon nitride film) to be described later is deposited.The treatment chamber 302 a and treatment chamber 302 b are connectedvia the load lock chamber 301, so the substrate can be transported tothe treatment chamber 302 b without vacuum breakdown after ammoniaplasma treatment, and ammonia plasma treatment and forming of the capfilm may be performed continuously.

Next, ammonia plasma treatment is performed on the substrate 1 using theaforesaid plasma treatment apparatus. The substrate 1 is transportedinto the load lock chamber 301 by the robot 304 from the cassetteinterface 303. The load lock chamber 301 is evacuated until the pressureis sufficiently reduced, and the substrate 1 is then transported to thetreatment chamber 302 a by the robot 304.

The gate valve 305 of the treatment chamber 302 is closed, and afterevacuating the treatment chamber 302 a until it is at a sufficientdegree of vacuum, ammonia gas is introduced to the treatment chambers302 a and is maintained at a predetermined pressure by pressureadjustment.

Subsequently, as shown in FIG. 16, an electric field is applied to theelectrode 309 from the high frequency power supply, and the surface ofthe substrate 1 is plasma treated. After a predetermined time haselapsed, the high frequency field is stopped and the plasma is stopped.Subsequently, the interior of the treatment chamber 302 a is evacuated,the gate valve 305 is opened and the substrate 1 is transported to theload lock chamber 301 by the robot 304. The load lock chamber 301 ismaintained at a high level of vacuum so that the surface of thesubstrate 1 is not exposed to the atmosphere.

When the size of the substrate 1 is eight inches about 20 cm), forexample, plasma treatment conditions may be pressure 5.0 Torr(=6.6661×10² Pa), RF power 600 W, substrate temperature 400° C., ammoniaflow rate 200 sccm and treatment time 10 seconds. The inter-electrodedistance was 600 mils. The plasma treatment conditions are of course notthe limited to those shown here.

According to experiments performed by the Inventors, the higher thepressure, the more the plasma damage can be reduced, the higher thesubstrate temperature is; while the scatter in the substrate regardingTDDB life is reduced and longer will be the life that is obtained. Itwas also observed that a hillock occurs more easily on the Cu surface,the higher the substrate temperature is, the larger the RF power is andthe longer the treatment time is. In view of these observations and thescatter in the conditions due to the construction of the apparatus, thepressure may be set to 0.5-6 Torr (=0.6666 1×10² to 7.99932×10² Pa), theRF power to 300-600 W, the substrate temperature to 350-450° C., theammonia flow rate to 20-500 sccm, the treatment time to 5-180 seconds,and the inter-electrode distance to 300-600 mils.

By performing plasma treatment on the surface of the copperinterconnections 46 a to 46 e and silicon oxide film 39, silicon nitridefilms of base layer material may be formed in very thin regions of thesurfaces of the copper interconnections 46 a to 46 e and silicon oxidefilm. Hence, the adhesion between the cap film (silicon nitride film),which will be described next, the Cu interconnections 46 a to 46 e andthe silicon oxide film 39 can be improved, and TDDB life can beremarkably enhanced.

This point will be described in more detail later together with ananalysis of the experimental results obtained by the Inventors.

Next, the substrate 1 is transported to the treatment chamber 302 busing the robot 304. The gate valve 305 b of the treatment chamber 302 bis closed, and after evacuating the treatment chamber 302 b to asufficient degree of vacuum, a mixture of silane (SiH₄), ammonia andnitrogen is introduced to the treatment chamber 302 b, and the pressureis maintained at a predetermined pressure by performing pressureadjustment. Subsequently, a plasma is generated by applying an electricfield to the electrode 309 from the high frequency power supply; and, asshown in FIG. 17, a silicon nitride film 47 (cap film) is deposited overthe surface of the Cu interconnections 46 a to 46 e and silicon nitridefilm 39. After a predetermined time has elapsed, the high frequencyfield is stopped and the plasma is stopped. Subsequently, the interiorof the processing chamber 302 b is evacuated, the gate valve 305 isopened and the substrate 1 is transported to the load lock chamber 301by the robot 304. The substrate 1 is further discharged into thecassette interface 303 by the robot 304.

The film thickness of the silicon nitride film 47 may be 50 nm, forexample. Subsequently, a silicon oxide film is formed so as to form aplug connecting a third interconnection layer and second interconnectionlayer (Cu interconnections 46 a to 46 e), the third and subsequentembedded copper interconnections being formed by the same method asdescribed above. FIG. 18 shows the overall flow of the process forforming the Cu interconnections 46 a to 46 e.

FIG. 19 shows an example of a CMOS-LSI in which interconnections areformed up to a seventh interconnection layer. The first interconnectionlayer (M1) comprises a tungsten film as described above. The filmthickness of the first interconnection layer and the line pitch(distance between centers of adjacent interconnections) are, forexample, of the order of 0.4 μm or 0.25 μm.

The second interconnection layer (M2) to the fifth interconnection layer(M5) are fabricated by the above method of forming Cu interconnections.The thickness of the TiN film of the second interconnection layer (M2)and third interconnection layer (M3) is, for example, of the order of0.05 μm, the thickness of the Cu film is, for example, of the order of0.35 μm, and the line width and line pitch are, for example, of theorder of 0.5 μm or 0.25 μm. The thickness of the TiN film of the fourthinterconnection layer (M4) and fifth interconnection layer (M5) is, forexample, of the order of 0.05 μm, the thickness of the Cu film is, forexample, of the order of 0.95 μm, and the line width and line pitch are,for example, of the order of 1.0 μm or 0.25 μm.

The sixth interconnection layer (M6) may, for example, have a threelayer composition of tungsten film, alumina film and tungsten film. Theseventh interconnection layer (M7) comprises, for example, an aluminumfilm. A pad electrode is formed on or a bonding wire is connected to apad of the seventh interconnection layer (M7), but this is not shown inthe diagram. One reason why the seventh interconnection layer (M7) iscomprised of a laminated film of alumina and tungsten, is that thislaminated film is used as the uppermost layer of ordinary semiconductorintegrated circuit devices not employing a Damascene interconnectionstructure, and connections to bump electrodes or bonding wires have beenfound to be reliable from experience.

The diameter of the through hole connecting the first interconnectionlayer M1 and second interconnection layer M2 may be of the order of 0.45μm or 0.25 μm, for example. The diameter of the through hole connectingthe second interconnection layer M2 and third interconnection layer M3may be of the order of 0.5 μm or 0.25 μm, for example. The diameter ofthe through hole connecting the third interconnection layer M3 andfourth interconnection layer M4 may be of the order of 0.5 μm or 0.25μm, for example. The diameter of the through hole connecting the fourthinterconnection layer M4 and fifth interconnection layer M5 may be ofthe order of 1.0 μm or 0.25 μm, for example. The diameter of the throughhole connecting the fifth interconnection layer M5 and sixthinterconnection layer M6 may be of the order of 0.5 μm or 0.25 μm, forexample.

According to this embodiment, the TDDB life is largely improved. FIG. 20is a graph showing the TDDB life of a TEG sample formed in the samelayer as the second interconnection layer M2 (Cu interconnections 46 ato 46 e) of this embodiment, the data for this embodiment being shown bya line A. As a comparison, TDDB life data (the line Ref) when ammoniaplasma treatment is not performed is also shown. As is clear from thediagram, according to this embodiment, a life improvement ofapproximately six orders of magnitude is found compared to thecomparison data.

FIG. 21 shows data (line B) when the silicon oxide film 39 used in thisembodiment is replaced by a hard silicon nitride film which has a finerconstruction. Even when the insulating film is replaced by siliconnitride, if ammonia plasma treatment is not performed, there is nodifference whatsoever from the case where a silicon oxide film is used(line Ref). On the other hand, if a silicon nitride film is used as theinsulating film and ammonia plasma treatment is performed, TDDB life isimproved more than in the present embodiment. However, the amount ofthis improvement is not large, and it is seen that the performing ofammonia plasma treatment is the determining factor.

This shows that the factors which determine TDDB life are morepredominantly governed by the interface of the insulating film than byits bulk.

The Inventors performed a surface examination of copper and siliconoxide films to analyze the mechanism whereby TDDB life is improved byammonium plasma treatment. The results of this analysis will now bedescribed.

FIG. 22( a)-FIG. 24( d) are graphs showing the results of an XPS (X-rayPhotoelectron Spectroscopy) of a Cu interconnection surface. FIGS. 22(a), 22(c), 23(a), 23(c), 24(a), and 24(c) show spectral results forCu2p, and FIGS. 22( b), 22(d), 23(b), 23(d), 24(b), and 24(d) show thespectral results for N1s.

FIGS. 22( a), 22(b) show the results of analyzing the Cu interconnectionsurface in the as-deposited state. Since a peak was observed due to Cu2pand the peak due to N1s is of the same level as background noise, it isseen that nitrogen is not present in the as-deposited Cu film. FIGS. 22(c), 22(d) show the results of analyzing the Cu interconnection surfaceimmediately after CMP alone was performed on the Cu film. Here, a N1speak is observed together with the peak due to Cu2p. As the slurrycontains BTA as described above, it may be conjectured that nitrogen inthe BTA remaining on the Cu surface is being observed. FIGS. 23( a),23(b) show the results of analyzing the Cu interconnection surface up tothe stage where post-washing is performed after CMP. There is no changein the Cu2p peak, but the N1s peak declines. This is probably due to theremoval of BTA by washing. FIGS. 23( c), 23(d) show the results ofanalyzing the Cu interconnection surface which was left for 24 hours inthe atmosphere after post-washing. A CuO peak is observed together withthe Cu2p peak. No change is however observed in the N1s peak. Thus,leaving the sample in the atmosphere caused oxidation of the Cu surfaceto produce CuO.

The results of analyzing the Cu interconnection surface when ammoniaplasma treatment was performed on the Cu interconnection oxidized inthis way are shown in FIGS. 24( a), 24(b). The peak due to CuO almostdisappears. On the other hand, the peak due to N1s is clearly visible.This is probably due to the fact the Cu surface was reduced, oxygen wasremoved and the surface was nitridized. As a comparison, the Cuinterconnection surface was analyzed when hydrogen annealing at 350° C.was performed on the oxidized Cu interconnection. The results are shownin FIGS. 24( c), 24(d). Comparing FIG. 24( c) with FIG. 24( a), the Cu2ppeak is closer to the as-deposited state (FIG. 22( a)), so it wouldappear that hydrogen annealing has a strong reducing action. On theother hand, the N1s peak is hardly observed at all, thus only the Cusurface is reduced by hydrogen annealing.

From the above results, it is seen that the surface of the Cuinterconnections 46 a to 46 e is reduced and a nitride film is formed byammonia plasma treatment. This nitride film prevents reaction betweensilane contained in the raw material gas and copper when the siliconnitride film is deposited after ammonia plasma treatment, and itevidently has the effect of suppressing the formation of coppersilicide. Prevention of silicide formation has the effect of suppressingan increase of the interconnection resistance.

FIGS. 25( a) to 25(f) are graphs showing the results of performing anXPS analysis of a silicon oxide film surface. FIGS. 26( a) to 26(d) andFIGS. 27( a) to (d) are graphs showing the result of performing a massspectrum (TDS-APIMS) analysis of a silicon oxide film. The analysis ofthe silicon oxide film was performed for the State up to washing afterCMP (profile C), the State where hydrogen plasma treatment was performedafter CMP post-washing (profile D), the state where ammonia plasmatreatment was performed after CMP post-washing (profile E), and thestate where nitrogen plasma treatment was performed after CMPpost-washing (profile F). The shift in the high-energy direction ofabout 1 eV in profile C is due to a charge-up effect.

FIGS. 25( a), 25(b) show observed data for Si2p spectra. FIG. 25( a)shows an analysis at a depth of about 10 nm, and FIG. 25( b) shows ananalysis at a depth of about 2 nm. FIGS. 25( c), 25(d), 25(e) showobserved data for N1s, O1s, C1s spectra.

In FIG. 25( b), a broad peak is observed (vicinity of 102 eV) at a lowenergy of hydrogen plasma treatment (profile D). This is probably due tothe presence of Si—H bonds, and the formation of Si—H on the siliconoxide film surface due to the hydrogen plasma treatment.

In FIG. 25( a), the peak at 105 eV for ammonia plasma treatment (profileE) and nitrogen plasma treatment (profile F) has become an asymmetricalpeak broadened towards the low energy side. The peak in the asymmetricalpart (103.5 eV) is probably due to Si—O—N bonds. It may be conjecturedthat the surface of the silicon oxide film was nitrided by the ammoniaplasma treatment and nitrogen plasma treatment. Also, from a comparisonof FIG. 25( a) and FIG. 25( b), it appears that nitriding is stronger onthe surface. The nitriding due to ammonia plasma treatment and nitrogenplasma treatment can be confirmed also from FIG. 25( c).

In FIG. 25( e), in hydrogen plasma treatment (profile D), almost nocarbon is detected. This means that organic substances on the surfaceare removed by hydrogen plasma treatment. Also, the peak at 289 eV afterCMP (profile C) is thought to be due to C-0 bonds. It appears that someslurry remains after CMP.

FIG. 25( f) calculates the population ratio of Si peaks and N peaks, andshows an estimated value for the N amount. It would appear thateffectively the same amount of nitriding takes place in both ammoniaplasma treatment and nitrogen plasma treatment.

FIGS. 26( a), 26(b), 26(c), 26(d) are graphs which respectively show ameasure of mass number 41 (Ar—H), mass number 27 (C2H3), mass number 57(C4H9) and mass number 59 (C3H7O) FIGS. 27( a), 27(b), 27(c), 27(d) aregraphs which respectively show a measure of mass number 28 (Si, C2H4),mass number 44 (SiO, C3H6), mass number 29 (SiH, C2H5) and mass number31 (SiH3).

In FIG. 26( a), there is almost no difference in the hydrogen desorptionamount due to plasma treatment, and the desorption temperature ofhydrogen plasma treatment (profile D) is low at 520° C. compared toother cases where it is 560° C.

From FIGS. 26( a), 26(b), 26(c), desorption of organic substances can beobserved in all processes. However, in FIGS. 27( a)-27(d), peaks otherthan those due to desorption of organic substances are observed.Specifically, peaks at 300-400° C. are probably due to Si, SiO, SiH andSiH3. Comparing the diagrams, breakup of SiO is observed in hydrogen,ammonia and nitrogen plasma treatments, but breakup of SiH, SiH3 ishardly observed at all in ammonia plasma treatment. This is becauseSi—O—N bonds are formed by ammonia plasma treatment, and these break upat a relatively low energy. Regarding the energy required for breakup,this energy is highest for nitrogen plasma treatment, and effectivelyidentical for hydrogen plasma treatment and ammonia plasma treatment.

From these results, it appears that Si—OH and Si—O which give rise todangling bonds on the silicon oxide film surface are terminated by weakSi—O—N bonds due to ammonia plasma treatment. In the process for forminga silicon nitride film after ammonia plasma treatment, Si—O—N which ispresent only on the surface breaks up, and Si—O bonds in the bulk bondsfirmly to Si—N in the silicon nitride film to form a continuousinterface. This appears to be the mechanism whereby the adhesionproperties of the interface are improved. On the other hand, if ammoniaplasma treatment is not performed, the surface of the silicon oxide filmwhich originally comprises a large number of Si—OH bonds undergoes acondensation reaction with ammonia which is the raw material gas of thesilicon nitride film, and a large number of Si—O bonds leading todangling bonds appear to be formed. If large numbers of such danglingbonds are present at the interface between the silicon oxide film andthe silicon nitride film, they will form a leakage path, giving rise toa leakage current between the interconnections and causing insulationbreakdown.

From the above analysis, the surfaces of oxidized Cu interconnectionsare reduced by ammonia plasma treatment and converted to elemental Cu.This produces an electrical state which is more stable than that ofionized copper; and, since a continuous, strong film is formed at thesilicon oxide film/silicon nitride film interface, the leakage currentdecreases, and TDDB life is largely improved.

The Inventors took TEM photographs of the interface between theinterconnection layer and silicon nitride film (cap film) when ammoniaplasma treatment was performed and when it was not. As a result, in thecase of this embodiment where ammonia plasma treatment was performed, athin coating was found to be present at the interface. This film andcoating evidently comprise the aforesaid silicon nitride layer. On theother hand, when ammonia plasma treatment was not performed, thiscoating was not observed.

Further, according to this embodiment, the resistance of the Cuinterconnection can be decreased. FIG. 28 shows the measurement resultsof interconnection resistance when various types of treatment wereperformed. In the case of no treatment (no plasma treatment) or whenammonia plasma treatment was performed, a significantly lower value wasfound compared to other cases (hydrogen plasma treatment, hydrogenannealing, nitrogen plasma treatment). FIG. 29 and FIG. 30 show traceoutlines of TEM photographs of the interface between the Cuinterconnection and the cap film (silicon nitride film) when thesetreatments were carried out.

When no treatment is performed or in the case of ammonia plasmatreatment (FIG. 29), no special features are observed in the interface,but in the case of hydrogen annealing and nitrogen plasma treatment(FIG. 30), a copper silicide (CuSi) layer is formed at the interface. Itis probable that this silicide layer leads to an increase of theresistance. This silicide layer is formed by reaction with silane gaswhen the silicon nitride film is formed, but when ammonia plasmatreatment is carried out, a very thin nitride film is formed over the Cusurface, and this nitride film probably acts as a blocking layer whichprevents silicide formation. On the other hand, when the upper surfaceis merely reduced as in the case of hydrogen annealing, an active Cusurface is exposed which promotes reaction with silicon, and this wouldeasily lead to the formation of a silicide layer. In the case ofhydrogen plasma treatment (FIG. 30 at part (c)), no product at all isobserved at the interface. However, in many cases such products wouldnot be formed, and in the case of hydrogen plasma treatment, the amountof silicide formation is probably small.

From the above analysis results, the Inventors arrived for the firsttime at the following model which appears to represent the mechanismbehind the deterioration of TDDB life. FIG. 31( a) shows a schematicview of the mechanism of TDDB deterioration, and FIG. 31( b) shows theenergy band involved. Specifically, when the ammonia plasma treatment ofthis embodiment is not performed, copper oxide (CuO) is formed on thesurface of the Cu interconnection which influences subsequent surfaceprocesses, and copper silicide (a copper compound) is formed when thecap film (silicon nitride film 47) is formed. This copper oxide orcopper suicide is more easily ionized than pure copper, and the ionizedcopper drifts due to the field between interconnections so as to diffuseinto the insulating film between interconnections.

Further, when the ammonia plasma treatment of this embodiment is notperformed, a large amount of CMP damage, organic substances or danglingbonds occur at the interface between the insulating film (silicon oxidefilm 39) formed by the embedding of the copper interconnections, and thecap film (silicon nitride film 47), so the interface is discontinuousand has poor adhesion properties. These dangling bonds also assist thediffusion of copper ions, so copper ions drift and diffuse along theinterface. In other words, a leakage path is formed in the interfacebetween interconnections. The leakage current flowing in the leak path,together with the long-term leakage effect and thermal stress due to thecurrent, lead to a rapid increase in the magnitude of the current andcauses insulation breakdown (reduction of TDDB life).

FIGS. 32( a), 32(b) show a schematic view of the mechanism for improvingTDDB life and the energy bands involved when the aforesaid ammoniaplasma treatment is performed. In this embodiment, as ammonia plasmatreatment is applied to the surface of the Cu interconnections 46 a to46 e, the oxide layer on the surface of the Cu interconnections 46 a to46 e is reduced and removed, and a thin nitride film is formed over thesurface of the Cu interconnections 46 a to 46 e. Hence, copper silicideis not formed when the silicon nitride film 47 is formed. As a result,the substances which mainly supply the copper ions leading to leakageand insulation breakdown are eliminated. In this embodiment, as theammonia plasma treatment is applied to the surface of the silicon oxidefilm 39, the connection with the silicon nitride film 47 becomescontinuous, the density of dangling bonds is reduced and leakage pathformation is suppressed. The surface of the silicon oxide film 39 canalso be kept clean. Therefore, in this embodiment, the generation ofcopper ions which lead to a reduction of TDDB life is suppressed, and ajoining interface is formed between the silicon oxide film 39 andsilicon nitride film 47 which can suppress diffusion of copper. In thisway, TDDB life can be enhanced.

From the aforesaid analysis, it would appear that TDDB life can probablybe improved even by hydrogen plasma treatment. Specifically, due tohydrogen plasma treatment, the Cu surface is reduced, and danglingbonds, such as Si—O or Si—OH, which are their precursors, are terminatedby Si—H. Thus, when the silicon nitride film is formed, Si—H, which is aweak bond on the surface, breaks up and is replaced by Si—N. In thisway, a continuous interface is formed between the silicon oxide film andsilicon nitride film, although the interconnection resistance increasesas noted above.

FIG. 33 is a graph showing TDDB life data when hydrogen plasma treatmentis performed. For reference purposes, the line Ref (no treatment) andthe line A (ammonia plasma treatment) are also shown. It is seen that inhydrogen plasma treatment (line C), TDDB life is vastly improved. In thecase of hydrogen plasma treatment, it might be expected that there wouldbe less plasma damage, and this might be expected to be extremely usefulwhen another material can be used as the cap film instead of the siliconnitride film which does not give reaction products with Cu. In nitrogenplasma treatment (line D), TDDB life declines on the other hand. As canbe seen also from FIGS. 26( a) to 26(d) and FIGS. 27( a) to 27(d), thisis probably due to increased adhesion of organic substances caused bythe nitrogen plasma treatment.

In this embodiment, adhesion properties between the Cu interconnections46 a-46, silicon oxide film 39 and cap film 47 are improved, so thepeeling strength at the interface increases, and the margin becomeslarger.

The invention is not limited to single gases, such as ammonia andhydrogen, and treatment may be performed using mixed gas plasmas withinert gases, such as nitrogen, argon and helium. More specifically, gasmixtures of ammonia with hydrogen, nitrogen, argon or helium, or gasmixtures of hydrogen with ammonia, nitrogen, argon or helium may beused. Further, gas mixtures of multi-element systems may also be usedcomprising three or four elements selected from these gases. In thiscase, the amount of hydrogen or ammonia, or the sum of hydrogen andammonia, must be at least 5% relative to the total flow rate (mass flowrate).

EMBODIMENT 2

A method of fabricating a CMOS-LSI according to a second embodiment ofthis invention will now be described with reference to a processsequence shown FIG. 34 to FIG. 43.

The initial steps of the method of fabrication according to this secondembodiment are identical to the steps shown in FIG. 1 to FIG. 8 ofEmbodiment 1. In other words, the steps of the method are the same up tothe Cu film deposition step. For this reason, only the processesfollowing the CMP step will be described in detail.

FIG. 34 is a schematic view showing the overall construction of a CMPapparatus using an embedded Cu interconnection. As shown in the figure,the CMP apparatus 400 comprises a polishing treatment part 401 and apost-washing part 402 provided in a later stage. Two platens (firstplaten 403A, second platen 403B) which perform polishing treatment ofthe wafer (substrate) 1, a clean station 404 which performs preliminarywashing of the substrate 1 when the polishing step is completed andgives anticorrosion treatment to the surface, and a rotating arm 405which displaces the substrate 1 between the loader 406, first platen403A, second platen 403B, clean station 404 and unloader 407, areprovided in the polishing treatment part 401.

In the later stage of the polishing treatment part 401, the post-washingpart 402 is provided which scrub-washes the surface of the substrate 1for which preliminary washing has been completed. In the post-washingpart 402, a loader 408, first washing part 409A, second washing part409B, spin drier 410 and unloader 411 are provided. Further, to preventthe surface of the substrate 1 from being irradiated by light while itis being washed, the whole of the post-washing part 402 is enclosed by ashielding wall 430 so that the interior is maintained in the dark at 180Lux, or preferably 100 Lux or less. This is because, when lightirradiates a surface of the substrate 1 on which a polishing solutionhas adhered in the wet state, a short-circuit current flows in the pnjunction due to the photo-induced current in the silicon, and Cu ionsdissociate from the surface of the Cu interconnection connected to the pside (+ side) of the pn junction, which causes interconnectioncorrosion.

As shown in FIG. 35, the first platen 403A is rotated in a horizontalplane by a drive mechanism 412 provided underneath it. A polishing pad413 formed by attaching a synthetic resin, such as polyurethane, havingplural air holes is evenly attached to the upper surface of the firstplaten 403A. A wafer carrier 415, which performs an up/down motion andis rotated in a horizontal plane by a drive mechanism 414, is disposedabove the first platen 403A. The substrate 1 is held, so that its mainface (surface to be polished) is facing downwards, by a wafer chuck 416and retainer ring 417 provided at the lower end of the wafer carrier415, and it is pushed against the polishing pad 413 under apredetermined load. A slurry (polishing fluid) S is supplied via a feedpipe 418 between the surface of the polishing pad 413 and the surface tobe polished of the substrate 1, and the surface to be polished of thesubstrate 1 is chemically and mechanically polished therewith. A dresser420, which performs an up/down motion and is rotated in a horizontalplane by a drive mechanism 419, is disposed above the first platen 403A.A base material on which diamond particles are deposited is attached atthe lower end of the dresser 420, the surface of the polishing pad 413being periodically machined by this base material to prevent blockingdue to abrasive polishing particles. The second platen 403B has aneffectively identical construction to the first platen 403A except thattwo slurry feed pipes 418A, 418B are provided.

To form the Cu interconnection using the CMP apparatus 400, thesubstrate 1 housed in the loader 406 is transported to the polishingtreatment part 401 by the rotating arm 405; and, as shown in FIG. 36,above the first platen 403A, chemical mechanical polishing (abrasiveparticle-free chemical mechanical polishing) (first step CMP) isperformed using a slurry not containing abrasive particles to remove theCu film 46 outside the interconnection slots 40 to 44 (FIG. 37).

Here, abrasive particle-free chemical mechanical polishing refers tochemical mechanical polishing using a polishing fluid (slurry) whereinthe content of abrasive particles including alumina and silica does notexceed 0.5 wt %. In the polishing fluid, it is preferred that thecontent of abrasive particles does not exceed 0.1 wt %, and morepreferable that it does not exceed 0.05 wt % or 0.01 wt %.

A polishing fluid is used having a pH which is adjusted so as to bewithin the Cu corrosion region, and the composition is adjusted so thatthe polishing selectivity ratio of the Cu film 46 relative to the TiNfilm 45 (barrier layer) is not less than 5. An example of such apolishing fluid is a slurry containing an oxidizing agent and an organicacid. The oxidizing agent may be hydrogen peroxide, aluminum hydroxide,ammonium nitrate or ammonium chloride, and the organic acid may becitric acid, malonic acid, fumaric acid, malic acid, adipic acid,benzoic acid, phthalic acid, tartaric acid, lactic acid or succinicacid. Of these, hydrogen peroxide does not contain any metal componentand is not a strong acid, so it is suitable as an oxidizing agent foruse in the polishing fluid. Citric acid is generally used as a foodadditive, has a low toxicity, does not give rise to much environmentalpollution, has no odor and has high solubility in water, so it issuitable as an organic acid for use in the polishing fluid. In thisembodiment, a polishing fluid is used wherein, for example, 5 vol % ofhydrogen peroxide and 0.03 wt % of citric acid are added to pure water,and the abrasive particle content is arranged to be less than 0.01 wt %.

When chemical mechanical polishing is performed with fluid, the Cusurface is first the aforesaid polishing oxidized by the oxidizingagent, and a thin oxide layer is formed on the surface. Next, asubstance is supplied which renders the oxidizing agent water-soluble,the oxide layer becomes water-soluble and dissolves, and the thicknessof the oxide layer decreases. The part where the oxide layer became thinis again exposed to the oxidizing substance so that the thickness of theoxide layer increases, and this reaction is repeated as chemicalmechanical polishing proceeds. This type of chemical mechanicalpolishing using an abrasive particle-free polishing fluid is describedin detail in Japanese Unexamined Patent Publication No. Hei9(1997)-299937 and Japanese Unexamined Patent Publication No. Hei10(1998)-317233 submitted by the Applicant et al. The polishingconditions are, for example, load=250 g/cm², wafer carrier rotationspeed=30 rpm, platen rotation speed=25 rpm, slurry flow rate=150 cc/min,and the polishing pad is a hard pad (IC1400) from Rodel Co. in the U.S.The endpoint of polishing is taken as the point when the Cu film 46 isremoved and the underlying TiN film 45 is exposed. This endpoint isdetected by detecting a rotation torque signal intensity of the platenor wafer carrier which varies when the polishing target changes from theCu film 46 to the TiN film 45. Alternatively, the endpoint may bedetected by opening a hole in part of the polishing pad and detectingthe spectral variation of reflected light from the wafer surface, or bydetecting the optical spectral variation of the slurry.

As shown in FIG. 37, by performing the above abrasive particle-freechemical mechanical polishing, the Cu film 46 outside theinterconnection slots 40 to 44 is almost entirely removed to expose theunderlying layer of the TiN film 45, but as shown in the enlargements ofFIGS. 38( a), 38(b), some of the Cu film 46 which could not be removedby this polishing may remain in depressions (shown by the arrow) in theTiN film 45 due to steps in the underlying layer.

Next, to remove the TiN film 45 outside the interconnection slots 40 to44 and the Cu film 46 remaining in some places on its upper surface, thesubstrate 1 is moved from the first platen 403A to the second platen403B shown in FIG. 34 to FIG. 36, and chemical mechanical polishing(abrasive particle chemical mechanical polishing) using a polishingfluid (slurry) containing abrasive particles (CMP of second step) isperformed. Here, the abrasive particle chemical mechanical polishingrefers to chemical mechanical polishing using a polishing fluid whereinthe content of abrasive particles including alumina or silica exceeds0.5 wt %. In this embodiment, the polishing fluid is a mixture of 5 vol% of hydrogen peroxide, 0.03 wt % of citric acid and 0.5 wt % ofabrasive particles with pure water, but this is not exhaustive. Thepolishing fluid is supplied to the polishing pad 413 of the secondplaten 403B via the slurry feed pipe 418A.

In this abrasive particle chemical mechanical polishing, after the Cufilm 46 which remains in some places on the upper surface of the TiNfilm 45 is removed, the TiN film 45 outside the interconnection slots 40to 44 is removed. In this process, polishing is performed underconditions wherein the polishing selectivity ratio of the Cu film 46relative to the TiN film 45 (barrier layer) is lower than that of theabrasive particle-free chemical mechanical polishing, e.g., underconditions where the selectivity ratio does not exceed 3, so as tosuppress polishing of the surface of the Cu film 46 inside theinterconnection slots 40 to 44.

The polishing conditions are, for example, load=120 g/cm² wafer carrierrotation speed=30 rpm, platen rotation speed=25 rpm, slurry flowrate=150 cc/min, and the polishing pad is IC1400 from Rodel Co. Thepolishing amount is equivalent to the film layer thickness of the TiNfilm 45, and the endpoint of polishing is controlled by the timecomputed from the film thickness and polishing speed of the TiN film 45.

As shown in FIG. 39, almost all of the TiN film 45 outside theinterconnection slots 40 to 44 is removed by performing the aboveabrasive particle chemical mechanical polishing to expose the underlyinglayer of silicon oxide film 39, but as shown in the enlargements ofFIGS. 40( a), 40(b), some of the TiN film 45 which could not be removedby the above polishing remains in depressions (shown by the arrow) ofthe silicon oxide film 39 due to steps in the layer underneath.

Next, while suppressing the polishing of the Cu film 46 inside theinterconnection slots 40 to 44 as much as possible, selective chemicalmechanical polishing (CMP of third step) is performed to remove the TiNfilm 45 (barrier layer) remaining in some parts on the silicon oxidefilm 39 outside the interconnection slots 40 to 44. This selectivechemical mechanical polishing is performed under conditions where thepolishing selectivity ratio of the TiN film 45 relative to the Cu film46 is at least 5 or more. Further, this chemical mechanical polishing isperformed under conditions wherein the ratio of the polishing speed ofthe silicon oxide film 39 relative to the polishing speed of the Cu film46 is larger than 1.

To perform the above selective chemical mechanical polishing, ananticorrosion agent is added to the polishing fluid comprising anabrasive particle content higher than 0.5 wt % such as is generally usedin the aforesaid abrasive particle chemical mechanical polishing. Theanticorrosion agent is a chemical which prevents or suppresses theprogress of polishing by forming an anticorrosive protection film on thesurface of the Cu film 46. Benzotriazole (BTA), benzotriazolederivatives, such as BTA carboxylic acid, dodecyl mercaptan, triazole ortolyl triazole, are used, and a particularly stable protection film isformed when BTA is used.

When BTA is used as the anticorrosion agent, its concentration dependson the type of slurry, but generally, a sufficient effect is obtained byadding 0.001-1 wt %, preferably 0.01-1 wt %, and more preferably 0.1-1wt % (three stages). In this embodiment, 0.1 wt % of BTA as theanticorrosion agent was mixed with the polishing fluid used in theabrasive particle chemical mechanical polishing of the second step, butthis is not exhaustive. Also, to avoid a decrease on the polishing speeddue to addition of the anticorrosion agent, polyacrylic acid,polymethacrylic acid, their ammonium salts or ethylenediaminetetraacetic acid (EDTA) can be added if necessary. Chemical mechanicalpolishing using a slurry containing such an anticorrosion agent isdescribed in detail in Japanese Unexamined Patent Publication No. Hei 10(1998)-209857, Japanese Unexamined Patent Publication No. Hei 9(1997)-299937 and Japanese Unexamined Patent Publication No. Hei 10(1998)-317233 submitted by the Applicant et al. After the abrasiveparticle chemical mechanical polishing (CMP of the second step) iscompleted, this selective chemical mechanical polishing (CMP of thethird step) is then performed on the second platen 403B of the CMPapparatus shown in FIG. 34-FIG. 36. The polishing fluid to which theanticorrosion agent is added, is supplied to the surface of thepolishing pad 413 via the aforesaid slurry feed pipe 418 b. Thepolishing conditions are, for example, load=120 g/cm², wafer carrierrotation speed=30 rpm, platen rotation speed=25 rpm, and slurry flowrate 190 cc/min.

As shown in FIG. 41 and FIGS. 42( a), 42(b), by performing the aboveselective chemical mechanical polishing, all of the TiN film 45 outsidethe interconnection slots 40 to 44 is removed, and the embedded Cuinterconnections 46 a to 46 e are formed inside the interconnectionslots 40 to 44.

A slurry residue containing particulates such as abrasive particles ormetal particles such as copper oxides adhere to the surface of thesubstrate 1 in which formation of the embedded Cu interconnections 46 ato 46 e is complete. To remove this slurry residue, in the clean station404 shown in FIG. 34, the substrate 1 is washed with pure watercontaining BTA. At this time, mechanical washing may be performedconcurrently by applying a high frequency vibration of 800 kHz or moreto the washing liquid to dislodge the slurry residue from the surface ofthe substrate 1. Next, to prevent drying of the surface, the substrate 1is transported while it is maintained in the wet state from thepolishing treatment part 401 to the post-washing part 402. In a firstwashing part 409A, scrub washing is performed using a washing liquidincluding 1 wt % of NH40H, and in a second washing part 409B, scrubwashing is performed using pure water. As described above, to preventcorrosion in the Cu interconnections 46 a to 46 e due to irradiation oflight on the surface of the substrate during washing, the whole sectionis covered by a shield wall 430.

The substrate 1 which has completed scrub washing (post-washing) isdried in the spin drier 410, and transported to the next step. Thesubsequent steps are identical to those of the first embodiment. FIG. 43is an overall flowchart of the processes used for forming the aforesaidCu interconnections 46 a to 46 e.

According to this embodiment, TDDB life can be improved more than in thefirst embodiment. FIG. 44 is a graph showing TDDB life in the case ofthis embodiment. The data for this embodiment is shown by the line E.For reference, data for no treatment (line Ref) and data for theabrasive particle chemical mechanical polishing (Embodiment 1) (line A)are shown simultaneously. TDDB characteristics are improved, as shown bythe line F, even if abrasive particle-free chemical mechanical polishingis performed without ammonia plasma treatment. This may be due to thefact that, in the case of abrasive particle-free chemical mechanicalpolishing, improvement of TDDB life results from less damage to thesilicon oxide film. In the case of abrasive particles, the slurrycontains abrasive particles (alumina, etc.) of 2-3 μm size (secondaryparticle diameters). Due to these abrasive particles, micro-scratchesoccur, and damage is done to the surface of the silicon oxide film 39.However, in the case of abrasive particle-free polishing, the slurrydoes not contain abrasive particles or only a very small amount of themeven if they are present, so that the damage can be largely reduced. Asa result, the TDDB characteristics are improved.

When the acid treatment (HF treatment) described in the next embodimentis performed in addition, the TDDB characteristics are further improved(line G). In this acid treatment, after CMP post-washing, the substrate1 is treated with an aqueous acid solution (e.g., aqueous HF solution),and ammonia plasma treatment is then performed. Due to the acidtreatment, the damaged layer on the surface is removed, interfaceadhesion characteristics are improved and TDDB life is improved.

EMBODIMENT 3

FIG. 45 is an overall flowchart of the process for forming the Cuinterconnections 46 a to 46 e of the third embodiment. As shown in thefigure, the process is identical to Embodiment 1 except that a HF orcitric acid washing step is inserted.

In HF washing, using brush scrub washing, for example, the HFconcentration may be 0.5% and the washing time may be 20 seconds.

Alternatively, instead of HF washing, citric acid washing may be used.In citric acid washing, using brush scrub washing, for example, thecitric acid concentration may be 5% and the washing time may be 45seconds.

By using HF or citric acid washing in this way, the damaged layer on thesurface due to CMP may be removed. Hence, the TDDB life can be improved.FIG. 46 is a graph showing TDDB life in the case of this embodiment. Thedata when citric acid is used in the case of this embodiment is shown bythe line H, and the data when HF washing is used is the line 1. Forreference, no treatment (line Ref) and the data of Embodiment 1 (line A)are shown simultaneously. The TDDB characteristics are improved, asshown by the line J, even if HF washing is performed alone withoutammonia plasma treatment. This is probably because the interfacecharacteristics are improved due to removal of the damaged layer.

EMBODIMENT 4

FIG. 47-FIG. 49 are plan views and sectional views showing a method offabricating the semiconductor integrated device according to a fourthembodiment of this invention. In FIG. 47 to FIG. 49, only theinterconnection part is shown.

As shown in FIG. 47, an insulating film 502 for forming interconnectionsis formed over an insulating film 501, and this insulating film 502 isembedded to form a copper interconnection 503. The method of forming thecopper interconnection 503 is identical to that of Embodiments 1-3.

Further, a silicon oxide film (TEOS oxide film) 506 is formed by plasmaCVD using a silicon nitride film 504, a low dielectric constant siliconoxide film 505 and TEOS as the raw material gas.

The low dielectric constant silicon oxide film 505 comprises a siliconoxide insulating film having a specific dielectric constant (6) notexceeding 3.0, such as for example by a coating insulating filmcomprising an inorganic SOG film having hydrogen silsesquioxane as a rawmaterial or an organic SOG film having tetraalkoxysilane+alkylalkoxysilane as a raw material, or a fluorocarbon polymer film formed byplasma CVD. By using this low dielectric constant silicon oxide film,the parasitic capacitance between interconnections is reduced andproblems of interconnection delay are avoided.

Next, in the pattern shown in FIG. 48( a), and as shown in FIG. 48( b),connecting holes 507 are formed. Photolithography and etching are usedto form the connecting holes 507. However, the dielectric constantsilicon oxide film 505 has a film structure with an uneven surface, andhas many Si—OH bonds. It has been found by experience that due to this,the film quality of the film formed as the upper layer and the state ofthe interface are poor. It has also been found from experience that ifthe barrier film (titanium nitride) described in the next step is formedas it is without treatment, the TDDB characteristics are poor.Therefore, the ammonia plasma treatment described in Embodiment 1 isapplied to the exposed part of the silicon oxide film 505 in theconnecting holes 507. As a result, the Si—OH bonds on the surface areimproved and are transformed into SI—O—N bonds as described inEmbodiment 1.

Next, as shown in FIG. 49, a plug 508 including titanium nitride andtungsten is formed in the connecting holes 507. When this titaniumnitride is deposited, the Si—O—N bonds break away as in Embodiment 1,the interface between titanium nitride and the low dielectric constantsilicon-oxide film 505 is improved, and the connectivity is improved.

The plasma treatment in the connecting holes may of course be appliedalso to the interconnection slots.

Instead of ammonia plasma treatment, a plasma treatment may be performedwith a mixture of nitrogen, argon and helium.

It may be that in an ashing step to remove the photoresist film afterforming the connecting holes 507, the surfaces of the interconnections503 in the bases of the connecting holes 507 are oxidized. To removethis oxide layer, a technique has been disclosed in Japanese UnexaminedPatent Publication No. Hei 11(1999)-16912.

The low dielectric constant silicon oxide film 505 is defined as asilicon oxide film having a lower dielectric constant than the siliconoxide film (for example, TEOS oxide film) contained in the protectionlayer formed as a passivation film.

EMBODIMENT 5

The method of forming the embedded Cu interconnections 46 a to 46 e maybe applied also to the formation of embedded Cu interconnections usingthe Dual Damascene method. In this case, after forming the first layerof W interconnections 24 to 30, as shown in FIG. 50, the silicon oxidefilm 31 having a film thickness of approximately 1200 nm, the thinsilicon nitride film 38 having a film thickness of approximately 50 nmand the silicon oxide film 39 having a film thickness of approximately350 nm, are first formed by plasma CVD over the first layer of the Winterconnections 24 to 30.

Next, as shown in FIG. 51, after progressively removing the siliconoxide film 39, silicon nitride film 38 and silicon oxide film 31overlying the first layer of the W interconnections 24, 26, 27, 29, 30by dry etching using a photoresist film as a mask, as shown also inFIGS. 52( a), 52(b), interconnection slots 50 to 54 with through holesare formed by removing the silicon oxide film 39 by dry etching usingthe silicon nitride film 38 as an etching stopper using anotherphotoresist film as a mask.

Next, as shown in FIG. 53, after depositing the thin TiN film 45 havinga film thickness of approximately 50 nm over the silicon oxide film 39,including the interior of the interconnection slots 50 to 54, the Cufilm 46 having a film thickness sufficiently larger than the depth ofthe interconnection slots 50 to 54 is deposited over the TiN film 45.Since the interconnection slots 50 to 54 with through holes have alarger aspect ratio than the interconnection slots 40 to 44, the TiNfilm 45 is deposited by CVD. Also, the Cu film 46 is deposited byrepeating sputtering two or more times. It may be formed by CVD,electrolysis plating or non-electrolysis plating. If the Cu film 46 isformed by plating, a step is required for forming a Cu seed layerunderneath the interconnection slots 50 to 54 by sputtering or the like.

Next, as shown in FIG. 54, the Cu film 46 and TiN film 45 outside theinterconnection slots 50 to 54 are removed by the aforesaid abrasiveparticle-free chemical mechanical polishing, abrasive particle chemicalmechanical polishing and selective chemical mechanical polishing, andthe embedded Cu interconnections 46 a to 46 e are formed inside theinterconnection slots 50 to 54. The remaining steps are identical to themethod of forming the embedded Cu interconnections 46 a to 46 e usingthe aforesaid Single Damascene method.

EMBODIMENT 6

As described above, it is commonly known that when Cu is used as aninterconnection material, the TDDB life is remarkably shorter than whenother is metal materials (e.g., aluminum and tungsten) are used. FIG. 55is a graph showing measured TDDB characteristic data for Cuinterconnections, aluminum interconnections and tungsteninterconnections. The vertical axis is TDDB life, and the horizontalaxis is field strength.

Extrapolating the properties of aluminum interconnections (data A) andtungsten interconnections (data B), the TDDB life at a field strength of0.2 MV/cm (as in normal use) far exceeds 3×10⁸ sec (10 years) which isthe development target of the Inventors. On the other hand,extrapolating the properties of Cu interconnections (data C), it is seenthat there is practically no margin regarding the development target of10 years.

In this experiment, the aluminium interconnections were formed bypatterning using film deposition and photolithography, while thetungsten interconnections were formed by an identical Damascene methodto that of the Cu interconnections. Specifically, the only differencebetween the Cu interconnections and tungsten interconnections is thematerial, there being no difference in structure. The remarkabledifference in TDDB characteristics despite this must therefore be due tothe difference in interconnection material. The TDDB characteristicsshow data obtained at a temperature of 140° C.

It is generally considered that the reason for the deterioration of theTDDB life is that Cu used as the interconnection material diffuses intothe surrounding area, and this lowers the installation breakdown voltagebetween interconnections. Therefore, concerning the use of Cuinterconnections, a barrier film would appear necessary to preventdiffusion of Cu. However, as interconnections become finer, theproportion of cross-sectional area of the high resistance barrier filmin the cross-sectional area of the interconnections increases, theinterconnection resistance increases, and the advantage of applyingcopper as an interconnection material becomes less.

Therefore, the Inventors performed fresh experiments and studies on thecopper diffusion phenomenon. As a result, the Inventors discovered, forthe first time, the actual mechanism behind the copper diffusionphenomenon as described above. Specifically, concerning the copper inthe interconnections, drifting and diffusion of ionized copper fromcopper oxide or copper silicide at the electric potential between theinterconnections is a far more important a factor than atomic copper.Also, the diffusion occurs predominantly between the insulating filmformed by the copper interconnections and the cap film. Specifically,copper oxide or copper suicide is formed on the surface of the copperinterconnections, copper ions are formed from these copper compounds,the ionized copper drifts and diffuses due to the field betweeninterconnections along the interface between the insulating film formingthe interconnections and the cap film, and the diffused-copper atomsincrease the leakage current. This increase in the leakage currentincreases the thermal stress, finally causing insulation breakdown onthe leakage path and affecting the TDDB life.

FIG. 56 is a graph showing the Si content in the copper interconnectionswhen various surface treatments are performed (ammonia plasma treatment,hydrogen plasma treatment, hydrogen annealing, nitrogen plasmatreatment), and when no treatment is performed. These test results wereobtained from a test performed after a step for forming the aforesaidcopper interconnections (including the TiN film (barrier film)), theaforesaid washing step, the aforesaid surface treatment steps, the stepfor forming the aforesaid cap film and a step for forming the interlayerinsulating film. It is thought that the same effect as that of Si wouldbe obtained from other impurities, such as oxygen or sulfur.

The copper silicide in the surface treatments mainly arises from setflow when the cap film (silicon nitride) is formed, as described above.In the hydrogen annealing treatment and nitrogen plasma treatment whenthis test is performed, the Si content in the vicinity of the surface (dapprox. 10-60 nm) and inside (d=approx. 90-300 nm) of the Cuinterconnections is larger than in the case of ammonia plasma treatmentor hydrogen plasma treatment. In particular, it is seen to be extremelyhigh in the vicinity of the surface. In this processing, the TDDBcharacteristics were poor as shown in FIG. 33.

On the other hand, the Si content in the vicinity of the surface of andinside the Cu interconnections is low in ammonia plasma treatment orhydrogen plasma treatment when this test is performed, compared withhydrogen annealing treatment and nitrogen plasma treatment. Inparticular, it is extremely low in the vicinity of the surface.Specifically, in this processing, the impurity content in the Cuinterconnections is low, the degree of cleanliness of the surface of theinsulating film in which the interconnection slots are formed is high,and there are few dangling bonds on the surface of the insulating filmin which the interconnection slots are formed. Therefore, as shown inFIG. 33, the TDDB characteristics were good. Thus, when there is a TiNfilm (conducting barrier film), the TDDB characteristics are determinedonly by the effect of the interface.

From this fresh viewpoint, the Inventors discovered for the first timethat it was possible to form a film of neutral Cu which is not ionizedin the side walls and bottom of the interconnection slots (increasingthe purity of the copper), to perform ammonia plasma treatment orhydrogen plasma treatment, or, by combining this with CMP or theaforesaid washing treatment, to improve the TDDB life of thesemiconductor integrated circuit device comprising Cu interconnectionseven if the film thickness of the barrier film was less than 10 nm, orwhen there was no barrier film at all.

Herein, FIG. 57 shows the dependence of the interconnection resistance,i.e., (TiN.x (film thickness) nm/TiN 50 nm ratio), on the thickness ofthe TiN film, i.e., (barrier film). The figure shows measured values andtheoretical values (calculated values) of the interconnection resistancefor a slot shape wherein the line width is, for example, of the order of0.4 μm and 1.0 μm, and the depth of the interconnection slots is, forexample, of the order of 0.4 μm. The film thickness of the TiN film isthe film thickness of the bottom of the interconnection slot.

From FIG. 57, it can be seen that the interconnection resistancedecreases as the thickness of the TiN film (barrier film) decreases, andthat the calculated values essentially coincide with the measuredvalues. Therefore, as compared with the interconnection resistance whenthe TiN film thickness is 50 nm, when there is no TiN film, theinterconnection resistance largely decreases by about 19% when the linewidth is of the order of 0.4 μm, and by about 15% when the line width isof the order of 10 μm. It is also seen that even when the film width ofthe TiN film is of the order of 10 nm, the interconnection resistancecan be decreased by about 16% when the line width is of the order of 0.4μm and by about 12% when the line width is of the order of 1.0 μm.

FIG. 58 shows the TiN film dependence of the TDDB characteristics in thecase where the Cu interconnection is formed by long throw sputtering.From this figure, it is seen that when the film thickness of the TiNfilm is 10-50 nm, the TDDB characteristics are of the same order asthose described above. On the other hand, it is seen that compared tothe TDDB characteristics when the TiN film is of the order of 10-50 nm,the TDDB characteristics of samples where there is no TiN filmconsiderably exceed the new system targets (e.g., 0.2 MV/cm, 110° C., 10years=3×10⁸ sec) although the slope becomes gentler.

FIG. 59 shows TDDB characteristics in the presence and absence of heattreatment in Cu interconnections when there is no TiN film, and when thethickness of the TiN film is of the order of 10 nm. From this figure, itis seen that even for samples where there is no TiN film, the TDDBcharacteristics do not deteriorate, for example, with heat treatment at400□C for 3 hours.

From the test results shown in FIG. 58 and FIG. 59, it was discoveredfor the first time, by experiments carried out by the Inventors, thateven when there is no TiN film, i.e., even when interconnections areformed only of Cu, sufficient reliability can still be attained andpractical Cu interconnections can still be formed.

A specific example of the interconnection structure of the semiconductorintegrated circuit device of the sixth embodiment is shown in FIGS. 60(a) and 60(b), which are sectional views in which part of thesemiconductor integrated circuit device (first interconnection layer andsecond interconnection layer) which has been removed. FIG. 60( a) showsa point formed by the Single Damascene method, and FIG. 60( b) shows apoint formed by the Dual Damascene method. A silicon oxide film 48 isdeposited over a silicon nitride film 47. In FIG. 60( b), the siliconoxide film 31 b is deposited over a silicon oxide film 31 a and thetungsten interconnection 27 via a silicon nitride film 49. The case isshown where the through hole 34, through which part of the tippersurface of the W interconnection 27 is exposed, is formed in the siliconoxide film 31 b and silicon nitride film 49. In the followingdescription, only the first interconnection layer and secondinterconnection layer will be described for convenience, but it shall beunderstood that this invention applies not only to these parts and canbe applied also to other interconnection layer parts.

The line width (width of interconnection slot 42) and adjacent lineinterval (distance between opposite lateral surfaces of adjacent lines)is, for example, 0.4 μm or less. This is a semiconductor integratedcircuit device having an interconnection structure wherein the linewidth and adjacent line interval studied by the Inventors is 0.25 μm orless, or 0.2 μm, for example. The aspect ratio of the interconnectionslot 42 is 1, for example.

The thickness of the conducting barrier film represented by the TiN film45 is less than 10 nm, and preferably of the order of 6-7 nm, forexample. In the sixth embodiment, the TDDB characteristics can beimproved even when the film thickness of this TiN film 45 does notexceed 5 nm or does not exceed 3 nm, or even when it is of the order ofonly 2 nm. Here, the thickness of the TiN film 45 means the surface partwhere the film is deposited most thinly. Herein, in the film thicknessof the TiN film 45 in the interconnection slots (e.g., interconnectionslot 42) or connecting holes (e.g., through hole 34), the side walls aredeposited most thinly, and the thickness therefore means the thicknessof the TiN film 45 in the side walls. Further, in this case, thefollowing two structures may occur, for example. In one of thesestructures, in the side walls of the interconnection slots or connectingholes (including the bottom angle part of the slot or hole), thethickness of the part where the TiN film 45 is thinnest is the abovethickness (e.g., less than 10 nm, and preferably about 6-7 nm, 5 nm orless, 3 nm or less or about 2 nm). In the other case, in the side wallsof the interconnection slot or connecting holes, the thickness of thepart where the TiN film 45 is thickest is the above thickness (e.g.,less than 10 nm, and preferably about 6-7 nm, 5 nm or less, 3 nm or lessor about 2 nm).

By forming the TiN film 45 to have a thickness of less than 10 nm, asdescribed above, the adhesion of the TiN film 45 to the silicon oxidefilm 39 is better than that of the Cu film, so peeling of the Cu film 46can be prevented when CMP is performed. Compared to the case where theTiN film 45 is not provided (as described in Embodiment 8 hereafter),the interconnection resistance increases, but a highly reliable Cuinterconnection structure can be fabricated. Also, compared to the casewhere the TiN film 45 is not provided, the TDDB characteristics areimproved. This is probably because, when there is no TiN film 45, Cuimpacts the side wall of the interconnection slot 42 when the Cu film 46is formed and reacts with SiO₂, so a small amount of Cu ions isproduced. Even after heat treatment, the TDDB characteristics do notdeteriorate, so this minute Cu ion layer at the CU/SiO₂ interface hassome effect. Therefore, according to this embodiment, even the thin TiNfilm 45 of less than 10 nm acts as a barrier to the ionized Cu, and theTDDB characteristics are improved.

The concentration of components other than Cu in the Cu interconnectionsrepresented by the Cu interconnection 46 c, does not exceed 0.8 At %, or0.2 At %. According to measurement results obtained by the Inventors, itis possible to arrange it so that the concentration of components otherthan Cu does not exceed, for example, 0.08 At %, 0.05 At % or 0.02 At %.This value of the concentration of components other than Cu is a valuewhen the semiconductor chip is completed, i.e., when a semiconductorchip is cut out of the semiconductor wafer after a wafer process, and isa value computed assuming diffusion in the Cu interconnection due to theheat when the insulating film or metal film is formed (e.g., in the caseof tungsten, heat of about 450° C. when the film is formed), afterforming the Cu interconnection.

In an actual Cu interconnection, regarding components other than Cu,their concentration in the upper layer of the Cu interconnection (partwhere the cap film is in contact) is high, and these components areprobably distributed so that they gradually become sparser towards thecenter of the Cu interconnection. The components other than Cu are, forexample, silicon, oxygen or sulfur (sulfur may be present when Cuinterconnection is formed by plating), or any combination of these.

Instead of the silicon oxide films 31 a, 31 b, 31, 39, 48, the materialof the interlayer insulating film may be SiOF, organic SOG (Spin OnGlass) or PSG (Phospho Silicate Glass), for example. In the case of aninsulating material having a low dielectric constant, such as a SiOF orSOG film, the interconnection capacitance can be decreased, so theperformance of the semiconductor integrated circuit device can beimproved. Further, a PSG film has the function of preventing thediffusion of Cu, so the TDDB life can be further improved. Therefore,the reliability of the semiconductor integrated circuit device can bestill further improved.

Next, one example of forming the Cu interconnection structure accordingto the Single Damascene method will be described with reference to FIG.61( a)-FIG. 65( b). FIGS. 61( a), 62(a), 63(a), 64(a) and FIG. 65( a)show plan views of the essential parts during the process ofmanufacturing the semiconductor integrated circuit device, and FIGS. 61(b), 62(b), 63(b), 64(b) and FIG. 65( b) show sections taken along a lineA-A in FIGS. 61( a), 62(a), 63(a), 64(a) and FIG. 65( a), respectively.FIGS. 61( a), 62(a), 63(a), and 64(a) are plan views, the metal filmbeing shaded for ease of understanding the diagram.

First, after the steps of FIG. 1-FIG. 6 described in Embodiment 1, theinterconnection slot 42 is formed as shown in FIGS. 61( a), 61(b) in thesame way as was described with reference to FIG. 7. The upper surface ofthe plug 37 is exposed on the bottom surface of the interconnection slot42. Next, as shown in FIG. 62( b), a Ta film 45 a (conducting barrierfilm), for example, is deposited to a thickness of about 30 nmas-deposited film thickness, for example, by an identical sputteringmethod to that of Embodiment 1. In this step, the Ta film 45 a isdeposited at the thickest point or the thinnest point of the side wallsof the interconnection slot 40, for example, to less than 10 nm, orabout 6-7 nm. Herein, the conducting barrier film was Ta, but asdescribed above, TiN or another film may be used.

Subsequently, the Cu film 46 is deposited over the Ta film 45 a to athickness of, for example, about 300 nm as-deposited film thickness, byan identical sputtering method to that of Embodiment 1. The conditionsin this step may be as follows. The pressure may be 0.02 Pa, the DCpower may be 10 kW, the distance between the target and the substrate 1may be 300-400 nm, and the temperature may be room temperature.

In this embodiment, therefore, by depositing the Cu film 46 bysputtering, the production of compounds can be maintained at a very lowlevel compared to the CVD or plating methods. Also, the target used inthis step was oxygen-free Cu of high purity, for example, 99.999% (5N)or higher, or preferably 99.9999% (6N) or higher. Hence, theconcentration of Cu in the Cu film 46 when the film is formed is 99.999%or higher, or preferably 99.9999% or higher. Therefore, Cu of evenhigher purity can be deposited.

When the Ta film 45 a and Cu film 46 are deposited, the ordinarysputtering method may be used, but a sputtering method with highdirectivity, such as long throw sputtering or collimate sputtering, mayalso be used. In this case, the coverage of the interconnection slot 42by the metal film can be improved.

Next, hydrogen annealing treatment is performed. Due to this, the Cufilm 46 is well embedded in the interconnection slot 42. The conditionsin this step may be of the order of 475° C., 3 minutes, 26.6644×10² Paand 500 sccm, for example.

Next, as shown in FIGS. 63( a), 63(b), the Cu film 46 and Ta film 45 aare polished by a CMP method identical to that of the aforesaidEmbodiments 1 and 2, and the Cu film 46 c is formed by removing surplusparts. Next, an anticorrosion process identical to that of the aforesaidEmbodiments 1 and 2, and a cleaning treatment identical to that of theaforesaid Embodiments 1 and 3, are performed. Subsequently, the ammoniaplasma treatment or hydrogen plasma treatment described in Embodiment 1is performed on the surface of the insulating film 39 and Cuinterconnection 46 c, as shown by the dotted shading of FIG. 64( b).

When ammonia plasma treatment is performed, SiH bonds and SiN bonds areformed on the surface part of the silicon oxide film 39, so the quality,degree of cleanliness and electrical stability of the surface part ofthe silicon oxide film 39 can be improved, and the Cu diffusionpreventing ability can be improved. As described in the aforesaidEmbodiment 1, adhesion to the cap film can also be improved. Further, inthe surface part of the Cu film 46 c, CuN is formed. This CuN acts tostop bonding between silicon and oxygen in later steps, preventingformation of copper silicide and copper oxide and improving the purityof the copper. Therefore, Cu diffusion is prevented, and the TDDB lifeis enhanced. Moreover, the purity of the Cu is high, so the resistanceof the Cu interconnections can be decreased as intended when thesemiconductor chip is in the finished state. As a result, theperformance of the semiconductor integrated circuit device can beimproved.

On the other hand, when hydrogen plasma treatment is performed, SiHbonds are formed in the surface part of the silicon oxide film 39, so asubstantially identical effect is obtained to the case of ammonia plasmatreatment. According to experimental results obtained by the Inventors,in hydrogen plasma treatment, Cu reacts with silicon to the extent ofseveral % in the subsequent cap film forming step, but the leakagecurrent is largely reduced compared to the case of hydrogen annealing,nitrogen plasma treatment or no treatment, and the TDDB life can beenhanced. Further, the resistance of the Cu interconnections is pooreras compared to ammonia plasma treatment, but it is less than in the caseof hydrogen annealing or nitrogen plasma treatment.

Subsequently, as shown in FIGS. 65( a), 65(b), the silicon nitride film(cap film) 47 is deposited in the same way as in Embodiment 1. Followingthis, as shown in FIG. 60( a), the silicon nitride film 48 is depositedby plasma CVD using, for example, TEOS (tetraethoxysilane).

Next, an example of forming the Cu interconnection structure by the DualDamascene method will be described with reference to FIG. 66( a)-FIG.77( b). FIGS. 66( a), 67(a), 68(a), 69(a), 70(a), 71(a), 72(a), 73(a),74(a), 75(a), 76(a) and 77(a) show plan views of the essential partsduring the fabrication of the semiconductor integrated circuit device,and FIGS. 66( b), 67(b), 68(b), 69(b), 70(b), 71(b), 72(b), 73(b),74(b), 75(b), 76(b) and 77(b) show sectional views taken along line A-Ain FIGS. 66( a), 67(a), 68(a), 69(a), 70(a), 71(a), 72(a), 73(a), 74(a),75(a), 76(a) and 77(a), respectively. FIGS. 73( a), 74(a), 75(a) andFIG. 76( a) are plan views wherein the metal films have been shaded tomake the drawings easier to understand.

First, after the steps of FIG. 1-FIG. 5 described in Embodiment 1, andafter the step of FIG. 50 of Embodiment 5, a reflection prevention film65 is coated over the silicon oxide film 39 and a photoresist pattern 66is formed thereupon, as shown in FIG. 66( b). The photoresist pattern 66is a mask pattern for forming, for example, flat circular holes, and isformed by ordinary photolithography. Next, as shown in FIG. 67( b), thereflection prevention film 65 which remains exposed is removed by dryetching using the photoresist pattern 66 a mask, and the through hole 34is formed by removing the silicon oxide film 39, silicon nitride film 38and silicon oxide film 31 b by dry etching. The etching of the siliconoxide film 39, silicon nitride film 38 and silicon oxide film 31 b isfirst performed non-selectively, then the etching selection ratio of thesilicon oxide film and silicon nitride film is increased, and etching isperformed under conditions such that the silicon oxide film is removedmore easily than the silicon nitride film. As a result, the through hole34 is opened using the silicon nitride film 49 as an etching stopper.Therefore, at this stage, the silicon nitride film 49 is exposed at thebottom surface of the through hole 34.

Next, as shown in FIG. 68( b), the photoresist pattern 66 and reflectionprevention film 65 are removed by ashing, etc., and as shown in FIG. 69(b), a reflection prevention film 67 is coated over the whole surface ofthe silicon oxide film 39 so that it is embedded in the through hole 34.Next, as shown in FIG. 70( b), a photoresist pattern 68 is formed overthe reflection prevention film 67. The photoresist pattern 68 is a maskpattern for forming, for example, a flat band-shaped interconnectionslot, and is formed by ordinary photolithography. Subsequently, as shownin FIG. 71( b), the reflection prevention film 67 which remains exposedis removed by dry etching using the photoresist pattern 68 as a mask,and the interconnection slot 42 is formed by removing the silicon oxidefilm 39 by dry etching. In the etching of this silicon oxide film 39,the etching selectivity ratio of the silicon oxide film and siliconnitride film is increased, and etching is performed under conditionssuch that the silicon oxide film is removed more easily than the siliconnitride film. In this way, the interconnection slot 42 is formed usingthe silicon nitride film 38 as an etching stopper. Therefore, at thisstage, the silicon nitride film 38 is exposed on the bottom surface ofthe interconnection slot 42.

Next, as shown in FIG. 72( b), after removing the photoresist pattern 68and reflection prevention film 67 by ashing, etc., the silicon nitridefilms 38, 49 exposed at the base of the interconnection slot 42 andthrough hole 34 are selectively removed. In this etching step, theetching selectivity ratio of the silicon oxide film and silicon nitridefilm is increased, and etching is performed so that the silicon nitridefilm is removed more easily than the silicon oxide film. In this way, asshown in FIG. 73( b), part of the silicon oxide film 39 and Winterconnection 27 is exposed from the bottom surface of theinterconnection slot 42 and through hole 34. This is in order to make anelectrical connection between the W interconnection 27 and the upperlayer embedded interconnection. Also, by reducing the silicon nitridefilms 38, 49 which have a higher dielectric constant than the siliconoxide film as much as possible, it also serves to decrease theinterconnection capacitance. In this way, the interconnection slot 42and through hole 34 are formed.

Next, as shown in FIG. 74( b), the Ta film 45 a (conducting barrierfilm) is deposited by sputtering under identical conditions to theSingle Damascene method described in Embodiment 6. In this step, the Tafilm 45 a is deposited at the thickest point or the thinnest point ofthe side walls of the interconnection slot 40, for example, to less than10 nm, or about 6-7 nm. Herein, the conducting barrier film was Ta, butas described above, TiN or another film may be used.

Next, the Cu film 46 is deposited over the Ta film 45 a to the thicknessof, for example, about 150 nm as-deposited film thickness, by anidentical sputtering method to that of Embodiment 6. The target used inthis step was, for example, oxygen-free Cu of a high purity, forexample, 99.999% (5N) or higher, or preferably 99.9999% (6N) or higher.Hence, the concentration of Cu in the Cu film 46 when the film is formedis 99.999% or higher, or preferably 99.9999% or higher. Therefore, Cu ofhigh purity can be deposited over the bottom surface and side walls ofthe Cu interconnection.

Subsequently, the Cu film 46 is formed by electrolysis plating or thelike. The conditions when the Cu film 46 is embedded in the through hole34 by electrolysis plating are, for example, current density 0.5-1.0A/dm², approx. 40 seconds. The conditions when the Cu film 46 isembedded in the interconnection slot 42 are, for example, currentdensity 1.0-2.0 A/dm², approx. 140 seconds.

Next, hydrogen annealing is performed in the same way as in the SingleDamascene method described in Embodiment 6. This treatment may sometimesbe omitted.

Next, as shown in FIG. 75( b), the Cu film 46 c is formed by polishingthe Cu film 46 and Ta film 45 a by a CMP technique identical to thatdescribed in Embodiments 1 and 2 to remove excess material, and ananticorrosion treatment identical to that of Embodiments 1, 2 andwashing treatment identical to that of Embodiments 1-3 are performed.Subsequently, the ammonia plasma treatment or hydrogen plasma treatmentdescribed in Embodiment 1 are performed on the surface of the insulatingfilm 39 and Cu film 46 c, as shown by the dotted shading of FIG. 76( b).In this way, the same effect as that of the Single Damascene methoddescribed in Embodiment 6 can be obtained.

Subsequently, as shown in FIG. 77( b), the silicon nitride film (capfilm) 47 is deposited in the same way as in Embodiment 1, and as shownin FIG. 60( b), the silicon oxide film 48 is formed by plasma CVD or thelike using for example TEOS gas on the silicon nitride film 47.

In this Embodiment 6, in addition to the effect obtained by theconstruction of Embodiment 6, concerning structural parts which areidentical to those of the aforesaid Embodiments 1-5, identical effectsto those described in Embodiments 1-5 can be obtained.

EMBODIMENT 7

In Embodiment 7, after forming interconnection slots and connectingholes, the aforesaid ammonia plasma treatment or hydrogen plasmatreatment is performed. The Single Damascene method and Dual Damascenemethod are identical, so Embodiment 7 will be described with referenceto FIGS. 78( a), 78(b) and FIGS. 79( a), 79(b) taking the Dual Damascenemethod as an example. FIG. 78( a), FIG. 79( a) show plan views of theessential parts during the fabrication of the semiconductor integratedcircuit device, and FIG. 78( b), FIG. 79( b) show sectional views takenon line A-A in FIG. 78( a), FIG. 79( a), respectively. FIG. 78( a), FIG.79( a) are plan views wherein the metal films have been shaded to makethe drawings easier to understand.

In Embodiment 7, after performing the fabrication steps described withreference to FIG. 66( a)-FIG. 73( b) of the aforesaid Embodiment 6,ammonia plasma treatment or hydrogen plasma treatment is performed asshown by the dotted shading of FIG. 78( b).

When ammonia plasma treatment is performed, SiH bonds and SiN and bondsare formed on the surface of the silicon oxide film 39 in the side wallsof the interconnection slot 42, the upper surface of the silicon oxidefilm 31 b in the base part of the interconnection slot 42 and thesurface of the silicon oxide film 31 b in the side walls of the throughhole 34 (e.g., a thin silicon nitride film of less than 10 nm isformed). As a result, the quality, degree of cleanliness and electricalstability of the upper surface of the silicon oxide film 39, the surfaceof the silicon oxide film 39 in the side walls of the interconnectionslot 42, the upper surface of the silicon oxide film 31 b in the basepart of the interconnection slot 42 and the surface of the silicon oxidefilm 31 b in the side walls of the through hole 34, can be improved, andthe Cu diffusion preventing ability can be improved. As described in theaforesaid Embodiment 1, adhesion between the silicon oxide film 39 andthe cap film can also be improved. After performing ammonia plasmatreatment, the nitride film (in this case, WN film) formed over the Winterconnection 27 may also be removed by lightly performing dryetching.

On the other hand, when hydrogen plasma treatment is performed, SiHbonds are formed on the upper surface of the silicon oxide film 39, thesurface of the silicon oxide film 39 in the side walls of theinterconnection slot 42, the upper surface of the silicon oxide film 31b in the base part of the interconnection slot 42 and the surface of thesilicon oxide film 31 b in the side walls of the through hole 34. As aresult, a substantially identical effect to that of ammonia plasmatreatment is obtained.

Next, as shown in FIG. 79( b), the Ta film 45 a and Cu film 46 areformed in sequence from the bottom layer in the same way as inEmbodiment 6. The remaining steps are identical to those of Embodiment6, and will not be repeated.

In Embodiment 7, in addition to the effect obtained in Embodiment 6, byperforming ammonia plasma treatment or hydrogen plasma treatment also onthe side walls of the interconnection slot 42 and through hole 34, theTDDB life is further improved, so that the reliability and yield of thesemiconductor integrated circuit device can be further improved.

EMBODIMENT 8

A specific example of the interconnection structure of the semiconductorintegrated circuit device of Embodiment 8 will now be described withreference to FIGS. 80( a) and 80(b), which are sectional views showingpart of the semiconductor integrated circuit device. FIG. 80( a) shows apoint formed by the Single Damascene method, and FIG. 80( b) shows apoint formed by the Dual Damascene method.

In Embodiment 8, the conducting barrier film is not formed.Specifically, only Cu is embedded in the interconnection slot 42 orthrough hole 34. Therefore, the side walls and base part of the Cuinterconnection 46 c are effectively in direct contact with the siliconoxide film 39. However, when the method described in Embodiment 7 isused, the side walls and base part of the Cu interconnection 46 c aredirectly in contact with the thin silicon nitride film formed over theside walls and base part of the silicon oxide film 39 in theinterconnection slot 42 and through hole 34.

The concentration and distribution of components other than Curepresented by the Cu interconnection 46 c are identical to thosedescribed in Embodiment 6. The materials of the interlayer insulatingfilms used instead of the silicon oxide films 31 a, 31 b, 31, 39, 48 arealso identical. Further, dimensions, such as the line width (width ofthe interconnection slot 42) and adjacent line interval (distancebetween opposite lateral surfaces of adjacent interconnections), areidentical to those described with reference to FIGS. 60( a) and 60(b) ofEmbodiment 6.

In this Embodiment 8 also, as described in Embodiment 6, the TDDB lifecan be enhanced. Therefore, the yield and reliability of thesemiconductor integrated circuit device can be improved. In Embodiment8, the conducting barrier film is not provided and only the Cu film 46is embedded in the interconnection slot 42 and through hole 34, so thatthe interconnection resistance can be largely improved. Further,different interconnection layers are directly connected without theintermediary of the conducting barrier film (Ta film 45 a or TiN film45) (herein, a structure is shown as an example wherein the Cu film 46 cand W interconnection 27 are directly connected, but Cu interconnectionsin different interconnection layers may also be directly connected), sothat the connection resistance between different interconnection layerscan be largely reduced, and the resistance of fine through holes can bedecreased. Therefore, the performance of the semiconductor integratedcircuit device can be enhanced even if the interconnection slots 42 andthrough holes 34 become finer.

The method of forming this Cu interconnection structure is identical tothat of Embodiments 6 and 7. As an example, the method of forming the Cuinterconnection structure of Embodiment 8 by the Dual Damascene methodwill be described with reference to FIG. 81( a)-FIG. 84( b). FIGS. 81(a), 82(a), 83(a), and 84(a) show plan views of the essential partsduring the fabrication of the semiconductor integrated circuit device,and FIGS. 81( b), 82(b), 83(b), and 84(b) show sectional views taken ona line A-A in FIGS. 81( a), 82(a), 83(a), and 84(a), respectively. FIGS.81( a), 82(a), 83(a) are plan views wherein the metal films have beenshaded to make the drawings easier to understand.

In Embodiment 8, after performing the fabrication steps described withreference to FIG. 66( a)-FIG. 73( b) of the aforesaid Embodiment 6,ammonia plasma treatment or hydrogen plasma treatment is performed asshown by the dotted shading of FIG. 81( b).

When ammonia plasma treatment is performed, as in Embodiment 7, thequality, degree of cleanliness and electrical stability of the uppersurface of the silicon oxide film 39, the surface of the silicon oxidefilm 39 in the side walls of the interconnection slot 42, the uppersurface of the silicon oxide film 31 b in the base part of theinterconnection slot 42 and the surface of the silicon oxide film 31 bin the side walls of the through hole 34, can be improved, and the Cudiffusion preventing ability can be improved. As in the aforesaidEmbodiment 1, adhesion between the silicon oxide film 39 and the capfilm can also be improved. As in Embodiment 7, after performing ammoniaplasma treatment, the nitride film (in this case, WN film) formed overthe W interconnection 27 may also be removed by lightly performing dryetching.

Next, as shown in FIG. 82( b), the Cu film 46 of high purity isdeposited in the same way as in the Cu film forming step of Embodiment6. Specifically, in Embodiment 8, the Cu film 46 of high purity isdeposited directly over the silicon oxide film 39 (including theinterior of the interconnection slot 42 and through hole 34) withoutdepositing the conducting barrier film (Ta film 45 a or TiN film 45). Itmay be considered that the Cu film 46 embedded in the interconnectionslot 42 and through hole 34 is in direct contact with the thin siliconnitride film in its side walls and at its base. In this structure,therefore, it is probably difficult for Cu to ionize in the side wallsand at the base of the Cu film 46.

Subsequently, as in Embodiment 6, after the Cu film 46 is polished andremoved by CMP or the like, cleaning treatment is performed. In thisway, as shown in FIG. 83( a), the Cu film 46 c is formed. The Cu film 46c is basically formed of Cu.

Next, the above ammonia plasma treatment or hydrogen plasma treatment isperformed on the upper surface of the silicon oxide film 39 and theupper surface (exposed surface) of the Cu film 46 c, as shown by thedotted shading of FIG. 83( b). In this way, as in Embodiment 6, Cudiffusion can be prevented, and the TDDB life can be enhanced. Further,since the purity of Cu can be kept high, the resistance of the Cuinterconnection in the finished semiconductor chip can be reduced.

Next, as shown in FIG. 84( b), similar to Embodiment 6, the siliconnitride film (cap film) 47 is deposited in the same way as in Embodiment1, and the silicon oxide film 48 is deposited thereon by plasma CVDusing, for example, TEOS gas as shown in FIG. 80( b).

In this Embodiment 8, in addition to the effect of Embodiments 1-7, thefollowing effect is obtained. Since a conducting barrier film is notprovided, the resistance of the Cu interconnection 46 c can be largelyreduced. Therefore, the performance of the semiconductor integratedcircuit device can be improved.

This invention has been described by way of specific examples based onvarious embodiments, but the invention is not limited to theseembodiments, various modifications being possible within the scope andspirit of the appended claims.

For example, it will be understood that, although Embodiments 1-8 can ofcourse be used alone, they may be used in combination. For example,chemical mechanical polishing may be performed with an abrasiveparticle-free slurry using the technology of Embodiment 2, acidtreatment subsequently applied using the technology of Embodiment 3, andammonia, hydrogen or other plasma treatment performed using thetechnology of Embodiment 1.

In Embodiments 1-8, the formation of the silicon nitride film 47 afterammonia plasma treatment was performed continuously without a break inthe vacuum, but after the ammonia plasma treatment, a break in thevacuum state may be performed first, and the silicon nitride film 47formed later. If a break in the vacuum is not performed, the effect ofthe invention is further enhanced, but as a thin nitride layer is formedby ammonia plasma treatment, the formation of an oxide layer can besuppressed even if a break in the vacuum state is performed and the chipis exposed to the atmosphere. Therefore, even in the case of a vacuumbreak, the effect of this embodiment is still obtained to some extent.

In Embodiments 1-8, a case was described in which the Cu film was formedby sputtering, but if the conditions are such that the purity of Cu canbe kept high, plating or CVD may also be used instead of sputtering.

In the above description, a case was described in which this inventionas conceived by the Inventors was applied to CMOS-LSI technology, whichis the background of the invention, but the invention is not limited tothis field, and may be applied, for example, also to semiconductorintegrated circuit devices comprising memory circuits, such as DRAM(Dynamic Random Access Memory), SRAM (Static Random Access Memory),flash memory (EEPROM: Electric Erasable Programmable Read Only Memory)or FRAM (Ferroelectric Random Access Memory), semiconductor integratedcircuit devices comprising logic circuits such as microprocessors, ormixed semiconductor integrated circuit devices wherein the aforesaidmemory circuits and logic circuits are provided on the samesemiconductor substrate. This invention may also be applied tosemiconductor integrated circuit devices, semiconductor devices,electronic circuit devices or electronic devices having at least a finecopper interconnection structure.

Of the various aspects and features of the invention disclosed in thisapplication, the advantages obtained by representative examples may besimply described as follows.

(1) According to one feature disclosed in this application, by makingthe concentration of components other than copper in the embeddedinterconnection not more than 0.8 At. % in the finished semiconductorchip, the resistance of the embedded interconnection having copper asits main component can be reduced.

(2) According to another feature disclosed in this application, asregards the side wall part of the aforesaid depression, by making thethickness of the thickest part of the conducting barrier film less than10 nm, the resistance of the embedded interconnection having copper asits main component can be reduced.

(3) According to a further feature disclosed in this application, byproviding a construction in which there is no barrier film in theaforesaid depression, the resistance of the embedded interconnectionhaving copper as its main component can be reduced.

(4) According to still another feature disclosed in this application, bymaking the concentration of components other than copper in the embeddedinterconnection not more than 0.8 At. % in the finished semiconductorchip, the insulation breakdown resistance between embeddedinterconnections having copper as their main component can be improved.

(5) According to a still further feature disclosed in this application,by providing a step wherein, after removing a metal film by chemicalmechanical polishing to form an embedded interconnection layer, theupper surface of an insulating film and the embedded interconnectionlayer is plasma treated in an atmosphere of a gas having reducingproperties, and providing a step of forming a cap insulating film overthe insulating film and embedded metal interconnection layer after theplasma treatment, the insulation breakdown resistance between embeddedinterconnections having copper as their main component can be improved.

(6) According to yet another feature disclosed in this application, byproviding a step wherein, after removing a metal film by chemicalmechanical polishing to form an embedded interconnection layer, theupper surface of an insulating film and the embedded interconnectionlayer is plasma treated in an atmosphere of a gas having reducingproperties, and providing a step of forming a cap insulating film overthe insulating film and embedded metal interconnection layer after theplasma treatment, adhesion between the interconnection layer of theembedded interconnection having copper as its principal component andthe cap film can be improved.

(7) Due to the aforesaid features (1)-(6), the performance of thesemiconductor integrated circuit device comprising an embeddedinterconnection having copper as its main component, can be improved.

(8) Due to the aforesaid features (4)-(6), the reliability of thesemiconductor integrated circuit device comprising an embeddedinterconnection having copper as its main component, can be improved.

(9) Due to the aforesaid features (4)-(6), the yield of thesemiconductor integrated circuit device comprising an embeddedinterconnection having copper as its main component, can be improved.

1. A method of fabricating a semiconductor integrated circuit devicecomprising: (a) forming a first insulating film over a semiconductorsubstrate; (b) forming a groove in the second insulating film; (c) afterthe step (b), performing a first plasma treatment; (d) after the step(c), forming a barrier metal film over an inner surface of the grooveand a upper surface of the first insulating film; (e) forming a copperseed layer over the barrier metal layer; (f) forming a copper filmcontaining copper as its principal component on the copper seed layer soas to fill the groove; (g) removing the barrier metal film, the copperseed layer and the copper film formed on the copper seed layer outsidethe groove so as to leave a copper interconnection in the groove; (h)after the step (g), performing a second plasma treatment; and (i) afterthe step (h), forming an insulating barrier film on the exposed surfaceof the first insulating film and the upper surface of the copperinterconnection.
 2. A method of fabricating a semiconductor integratedcircuit device according to the claim 1, wherein, in the step (c), thefirst plasma treatment is an ammonia plasma treatment.
 3. A method offabricating a semiconductor integrated circuit device according to theclaim 2, wherein, in the step (c), an inner surface of the groove anupper surface of the first insulating film are nitrided by the ammoniaplasma treatment.
 4. A method of fabricating a semiconductor integratedcircuit device according to the claim 1, wherein, in the step (c), thefirst plasma treatment is an hydrogen plasma treatment.
 5. A method offabricating a semiconductor integrated circuit device according to theclaim 1, wherein, in the step (h), the second plasma treatment is anammonia plasma treatment.
 6. A method of fabricating a semiconductorintegrated circuit device according to the claim 1, wherein, in the step(h), the second plasma treatment is an hydrogen plasma treatment.
 7. Amethod of fabricating a semiconductor integrated circuit deviceaccording to the claim 1, further comprising a step; (j) after the step(f) and before the step (g), performing a hydrogen annealing treatment.8. A method of fabricating a semiconductor integrated circuit deviceaccording to the claim 1, wherein, in the step (f), the copper film isformed by electrolysis plating.
 9. A method of fabricating asemiconductor integrated circuit device according to the claim 1,wherein the barrier metal film includes a tantalum film.
 10. A method offabricating a semiconductor integrated circuit device according to theclaim 1, wherein the film thickness of the thinnest part of the barriermetal film in the groove is less than 10 nm.
 11. A method of fabricatinga semiconductor integrated circuit device according to the claim 1,wherein the film thickness of the thinnest part of the barrier metalfilm in the groove is less than 5 nm.
 12. A method of fabricating asemiconductor integrated circuit device according to the claim 1,wherein, in the step (e), the copper seed layer is formed by coppersputtering with a copper target having a purity of 99.999% or more. 13.A method of fabricating a semiconductor integrated circuit deviceaccording to the claim 1, wherein the total concentration of componentsother than copper in the copper interconnection, when step (h) iscompleted, does not exceed 0.8 At %.
 14. A method of fabricating asemiconductor integrated circuit device according to the claim 1,wherein a width of said groove is less than 0.4 μm.
 15. A method offabricating a semiconductor integrated circuit device according to theclaim 1, wherein a width of said groove is less than 0.2 μm.
 16. (dualD) A method of fabricating a semiconductor integrated circuit devicecomprising: (a) forming a first wiring over a semiconductor substrate;(b) forming a first insulating film over the first wiring; (c) forming asecond insulating film over the first insulting film; (d) forming agroove in the second insulating film and a hole in the first insulatingfilm, the hole being connected to the first wiring; (e) after the step(d), performing a first plasma treatment; (f) after the step (e),forming a barrier metal film over inner surfaces of the groove and thehole, over an upper surface of the second insulating film and over anupper surface of the first wiring; (g) forming a copper seed layer overthe barrier metal layer; (h) forming a copper film containing copper asits principal component on the copper seed layer so as to fill thegroove and the hole; (i) removing the barrier metal film, the copperseed layer and the copper film formed on the copper seed layer outsidethe groove and the hole so as to leave a copper interconnection in thegroove and the hole; (j) after the step (i), performing a second plasmatreatment; and (k) after the step (j), forming an insulating barrierfilm on the exposed surface of the second insulating film and the uppersurface of the copper interconnection.
 17. A method of fabricating asemiconductor integrated circuit device according to the claim 16,wherein, in the step (e), the first plasma treatment is an ammoniaplasma treatment.
 18. A method of fabricating a semiconductor integratedcircuit device according to the claim 17, wherein, in the step (e),inner surfaces of the groove and the hole and an upper surface of thesecond insulating film are nitrided by the ammonia plasma treatment. 19.A method of fabricating a semiconductor integrated circuit deviceaccording to the claim 16, wherein, in the step (e), the first plasmatreatment is an hydrogen plasma treatment.
 20. A method of fabricating asemiconductor integrated circuit device according to the claim 16,wherein, in the step (j), the second plasma treatment is an ammoniaplasma treatment.
 21. A method of fabricating a semiconductor integratedcircuit device according to the claim 16, wherein, in the step (j), thesecond plasma treatment is an hydrogen plasma treatment.
 22. A method offabricating a semiconductor integrated circuit device according to theclaim 16, further comprising a step; (l) after the step (h) and beforethe step (i), performing a hydrogen annealing treatment.
 23. A method offabricating a semiconductor integrated circuit device according to theclaim 16, further comprising a step; (m) after the step (e) and beforethe step (f), removing the upper surface of the first wiring byperforming a dry etching treatment.
 24. A method of fabricating asemiconductor integrated circuit device according to the claim 16,wherein, in the step (h), the copper film is formed by electrolysisplating.
 25. A method of fabricating a semiconductor integrated circuitdevice according to the claim 16, wherein the barrier metal filmincludes a tantalum film.
 26. A method of fabricating a semiconductorintegrated circuit device according to the claim 16, wherein the filmthickness of the thinnest part of the barrier metal film in the grooveand the hole is less than 10 nm.
 27. A method of fabricating asemiconductor integrated circuit device according to the claim 16,wherein the film thickness of the thinnest part of the barrier metalfilm in the groove and the hole is less than 5 nm.
 28. A method offabricating a semiconductor integrated circuit device according to theclaim 16, wherein, in the step (g), the copper seed layer is formed bycopper sputtering with a copper target having a purity of 99.999% ormore.
 29. A method of fabricating a semiconductor integrated circuitdevice according to the claim 16, wherein the total concentration ofcomponents other than copper in the copper interconnection, when step(j) is completed, does not exceed 0.8 At %.
 30. A method of fabricatinga semiconductor integrated circuit device according to the claim 16,wherein a width of said groove is less than 0.4 μm.
 31. A method offabricating a semiconductor integrated circuit device according to theclaim 16, wherein a width of said groove is less than 0.2 μm.